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-- $Id: nexys3lib.vhd 432 2011-11-25 20:16:28Z mueller $
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-- $Id: nexys3lib.vhd 509 2013-04-21 20:46:20Z mueller $
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--
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--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Tool versions: xst 13.1; ghdl 0.29
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-- Tool versions: xst 13.1; ghdl 0.29
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2013-04-21 509 1.1 add nexys3_cuff_aif, nexys3_fusp_cuff_aif
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-- 2011-11-25 432 1.0 Initial version
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-- 2011-11-25 432 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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O_PPCM_CE_N : out slbit; -- ppcm: ...
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O_PPCM_CE_N : out slbit; -- ppcm: ...
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O_PPCM_RST_N : out slbit -- ppcm: ...
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O_PPCM_RST_N : out slbit -- ppcm: ...
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);
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);
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end component;
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end component;
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component nexys3_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
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component nexys3_fusp_aif is -- NEXYS 3, abstract iface, base+fusp
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port (
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port (
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I_CLK100 : in slbit; -- 100 MHz clock
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I_CLK100 : in slbit; -- 100 MHz clock
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I_RXD : in slbit; -- receive data (board view)
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- n3 switches
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I_SWI : in slv8; -- n3 switches
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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O_FUSP_TXD : out slbit -- fusp: rs232 tx
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O_FUSP_TXD : out slbit -- fusp: rs232 tx
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);
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);
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end component;
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end component;
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component nexys3_cuff_aif is -- NEXYS 3, abstract iface, base+cuff
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port (
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I_CLK100 : in slbit; -- 100 MHz clock
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- n3 switches
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I_BTN : in slv5; -- n3 buttons
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O_LED : out slv8; -- n3 leds
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O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
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O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
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O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
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O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CRE : out slbit; -- cram: command register enable
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I_MEM_WAIT : in slbit; -- cram: mem wait
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O_MEM_ADDR : out slv23; -- cram: address lines
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IO_MEM_DATA : inout slv16; -- cram: data lines
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O_PPCM_CE_N : out slbit; -- ppcm: ...
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O_PPCM_RST_N : out slbit; -- ppcm: ...
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I_FX2_IFCLK : in slbit; -- fx2: interface clock
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O_FX2_FIFO : out slv2; -- fx2: fifo address
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I_FX2_FLAG : in slv4; -- fx2: fifo flags
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O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
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O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
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O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
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O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
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IO_FX2_DATA : inout slv8 -- fx2: data lines
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);
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end component;
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component nexys3_fusp_cuff_aif is -- NEXYS 3, abstract iface, +fusp+cuff
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port (
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I_CLK100 : in slbit; -- 100 MHz clock
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- n3 switches
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I_BTN : in slv5; -- n3 buttons
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O_LED : out slv8; -- n3 leds
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O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
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O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
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O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
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O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
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O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CRE : out slbit; -- cram: command register enable
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I_MEM_WAIT : in slbit; -- cram: mem wait
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O_MEM_ADDR : out slv23; -- cram: address lines
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IO_MEM_DATA : inout slv16; -- cram: data lines
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O_PPCM_CE_N : out slbit; -- ppcm: ...
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O_PPCM_RST_N : out slbit; -- ppcm: ...
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O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
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I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
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I_FUSP_RXD : in slbit; -- fusp: rs232 rx
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O_FUSP_TXD : out slbit; -- fusp: rs232 tx
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I_FX2_IFCLK : in slbit; -- fx2: interface clock
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O_FX2_FIFO : out slv2; -- fx2: fifo address
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I_FX2_FLAG : in slv4; -- fx2: fifo flags
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O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
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O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
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O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
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O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
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IO_FX2_DATA : inout slv8 -- fx2: data lines
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);
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end component;
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end package nexys3lib;
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end package nexys3lib;
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