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-- $Id: sys_w11a_n2.vhd 433 2011-11-27 22:04:39Z mueller $
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-- $Id: sys_w11a_n2.vhd 440 2011-12-18 20:08:09Z mueller $
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--
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--
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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--
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--
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-- Dependencies: vlib/xlib/dcm_sfs
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-- Dependencies: vlib/xlib/dcm_sfs
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-- vlib/genlib/clkdivce
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-- vlib/genlib/clkdivce
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-- bplib/bpgen/bp_rs232_2l4l_iob
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-- bplib/bpgen/bp_rs232_2l4l_iob
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-- bplib/bpgen/sn_humanio_rbus
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-- bplib/bpgen/sn_humanio_rbus
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-- vlib/rlink/rlink_base_serport
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-- vlib/rlink/rlink_sp1c
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-- vlib/rri/rb_sres_or_3
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-- vlib/rri/rb_sres_or_3
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-- w11a/pdp11_core_rbus
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-- w11a/pdp11_core_rbus
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-- w11a/pdp11_core
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-- w11a/pdp11_core
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-- w11a/pdp11_bram
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-- w11a/pdp11_bram
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-- vlib/nxcramlib/nx_cram_dummy
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-- vlib/nxcramlib/nx_cram_dummy
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.26-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.26-0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2011-12-18 440 13.1 O40d xc3s1200e-4 1450 4439 270 2740 ok: LP+PC+DL+II
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-- 2011-11-18 427 13.1 O40d xc3s1200e-4 1433 4374 242 2680 ok: LP+PC+DL+II
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-- 2011-11-18 427 13.1 O40d xc3s1200e-4 1433 4374 242 2680 ok: LP+PC+DL+II
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-- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II
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-- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II
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-- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
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-- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
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-- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II
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-- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II
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-- 2010-10-17 333 12.1 M53d xc3s1200e-4 1350 4541 242 2617 ok: LP+PC+DL+II
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-- 2010-10-17 333 12.1 M53d xc3s1200e-4 1350 4541 242 2617 ok: LP+PC+DL+II
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-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II
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-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II
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-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
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-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-12-18 440 1.2.7 use rlink_sp1c
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-- 2011-11-26 433 1.2.6 use nx_cram_(dummy|memctl_as) now
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-- 2011-11-26 433 1.2.6 use nx_cram_(dummy|memctl_as) now
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-- 2011-11-23 432 1.2.5 update O_FLA_CE_N usage
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-- 2011-11-23 432 1.2.5 update O_FLA_CE_N usage
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-- 2011-11-19 427 1.2.4 now numeric_std clean
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-- 2011-11-19 427 1.2.4 now numeric_std clean
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-- 2011-11-17 426 1.2.3 use dcm_sfs now
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-- 2011-11-17 426 1.2.3 use dcm_sfs now
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-- 2011-07-09 391 1.2.2 use now bp_rs232_2l4l_iob
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-- 2011-07-09 391 1.2.2 use now bp_rs232_2l4l_iob
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-- w11a test design for nexys2
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-- w11a test design for nexys2
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-- w11a + rlink + serport
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-- w11a + rlink + serport
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--
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--
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-- Usage of Nexys 2 Switches, Buttons, LEDs:
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-- Usage of Nexys 2 Switches, Buttons, LEDs:
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--
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--
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-- SWI(7:2): no function (only connected to sn_humanio_rbus)
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-- SWI(1): 1 enable XON
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-- SWI(0): 0 -> main board RS232 port
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-- SWI(0): 0 -> main board RS232 port
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-- 1 -> Pmod B/top RS232 port
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-- 1 -> Pmod B/top RS232 port
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--
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--
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-- LED(0:4): if cpugo=1 show cpu mode activity
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-- LED(7) MEM_ACT_W
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-- (0) user mode
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-- (6) MEM_ACT_R
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-- (1) supervisor mode
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-- (5) cmdbusy (all rlink access, mostly rdma)
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-- (2) kernel mode, wait
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-- (4:0): if cpugo=1 show cpu mode activity
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-- (3) kernel mode, pri=0
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-- (4) kernel mode, pri>0
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-- (4) kernel mode, pri>0
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-- (3) kernel mode, pri=0
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-- (2) kernel mode, wait
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-- (1) supervisor mode
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-- (0) user mode
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-- if cpugo=0 shows cpurust
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-- if cpugo=0 shows cpurust
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-- (3:0) cpurust code
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-- (3:0) cpurust code
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-- (4) '1'
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-- (4) '1'
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-- (5) cmdbusy (all rlink access, mostly rdma)
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-- (6) MEM_ACT_R
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-- (7) MEM_ACT_W
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--
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--
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-- DP(0): RXSD (inverted to signal activity)
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-- DP(3): not SER_MONI.txok (shows tx back preasure)
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-- DP(1): RTS_N (shows rx back preasure)
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-- DP(2): SER_MONI.txact (shows tx activity)
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-- DP(2): TXSD (inverted to signal activity)
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-- DP(1): not SER_MONI.rxok (shows rx back preasure)
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-- DP(3): CTS_N (shows tx back preasure)
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-- DP(0): SER_MONI.rxact (shows rx activity)
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.xlib.all;
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use work.xlib.all;
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use work.genlib.all;
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use work.genlib.all;
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use work.serport.all;
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use work.rblib.all;
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use work.rblib.all;
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use work.rlinklib.all;
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use work.rlinklib.all;
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use work.bpgenlib.all;
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use work.bpgenlib.all;
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use work.nxcramlib.all;
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use work.nxcramlib.all;
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use work.iblib.all;
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use work.iblib.all;
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signal DSP_DP : slv4 := (others=>'0');
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signal DSP_DP : slv4 := (others=>'0');
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signal RB_LAM : slv16 := (others=>'0');
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signal RB_LAM : slv16 := (others=>'0');
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signal RB_STAT : slv3 := (others=>'0');
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signal RB_STAT : slv3 := (others=>'0');
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signal SER_MONI : serport_moni_type := serport_moni_init;
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
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signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
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signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
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signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
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signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
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signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
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Line 315... |
O_LED => O_LED,
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O_LED => O_LED,
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O_ANO_N => O_ANO_N,
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O_ANO_N => O_ANO_N,
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O_SEG_N => O_SEG_N
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O_SEG_N => O_SEG_N
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);
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);
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RLINK : rlink_base_serport
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RLINK : rlink_sp1c
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generic map (
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generic map (
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ATOWIDTH => 6, -- 64 cycles access timeout
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ATOWIDTH => 6, -- 64 cycles access timeout
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ITOWIDTH => 6, -- 64 periods max idle timeout
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ITOWIDTH => 6, -- 64 periods max idle timeout
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CPREF => c_rlink_cpref,
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IFAWIDTH => 5, -- 32 word input fifo
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IFAWIDTH => 5, -- 32 word input fifo
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OFAWIDTH => 0, -- no output fifo
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OFAWIDTH => 5, -- 32 word output fifo
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ENAPIN_RLMON => sbcntl_sbf_rlmon,
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ENAPIN_RBMON => sbcntl_sbf_rbmon,
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CDWIDTH => 13,
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CDWIDTH => 13,
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CDINIT => sys_conf_ser2rri_cdinit)
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CDINIT => sys_conf_ser2rri_cdinit)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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CE_INT => CE_MSEC,
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CE_INT => CE_MSEC,
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RESET => RESET,
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RESET => RESET,
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ENAXON => SWI(1),
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ENAESC => SWI(1),
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RXSD => RXD,
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RXSD => RXD,
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TXSD => TXD,
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TXSD => TXD,
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CTS_N => CTS_N,
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CTS_N => CTS_N,
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RTS_N => RTS_N,
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RTS_N => RTS_N,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES,
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RB_SRES => RB_SRES,
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RB_LAM => RB_LAM,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT,
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RB_STAT => RB_STAT,
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RL_MONI => open,
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RL_MONI => open,
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RL_SER_MONI => open
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SER_MONI => SER_MONI
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);
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);
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RB_SRES_OR : rb_sres_or_3
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RB_SRES_OR : rb_sres_or_3
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port map (
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port map (
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RB_SRES_1 => RB_SRES_CPU,
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RB_SRES_1 => RB_SRES_CPU,
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| Line 544... |
Line 557... |
DISPREG => DISPREG
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DISPREG => DISPREG
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);
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);
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end generate IBD_MAXI;
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end generate IBD_MAXI;
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DSP_DAT(15 downto 0) <= DISPREG;
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DSP_DAT(15 downto 0) <= DISPREG;
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DSP_DP(0) <= not RXD;
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DSP_DP(1) <= RTS_N;
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DSP_DP(3) <= not SER_MONI.txok;
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DSP_DP(2) <= not TXD;
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DSP_DP(2) <= SER_MONI.txact;
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DSP_DP(3) <= CTS_N;
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DSP_DP(1) <= not SER_MONI.rxok;
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DSP_DP(0) <= SER_MONI.rxact;
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proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
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proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
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variable iled : slv8 := (others=>'0');
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variable iled : slv8 := (others=>'0');
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begin
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begin
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iled := (others=>'0');
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iled := (others=>'0');
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