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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [sys_gen/] [w11a/] [nexys2/] [sys_w11a_n2.vhd] - Diff between revs 19 and 20

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Rev 19 Rev 20
Line 1... Line 1... 
-- $Id: sys_w11a_n2.vhd 476 2013-01-26 22:23:53Z mueller $
 
-- $Id: sys_w11a_n2.vhd 509 2013-04-21 20:46:20Z mueller $
 
--
 
--
 
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 
-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 
--
 
--
 
-- This program is free software; you may redistribute and/or modify it under
 
-- This program is free software; you may redistribute and/or modify it under
 
-- the terms of the GNU General Public License as published by the Free
 
-- the terms of the GNU General Public License as published by the Free
 
-- Software Foundation, either version 2, or at your option any later version.
 
-- Software Foundation, either version 2, or at your option any later version.
 
--
 
--
Line 17... Line 17... 
--
 
--
 
-- Dependencies:   vlib/xlib/dcm_sfs
 
-- Dependencies:   vlib/xlib/dcm_sfs
 
--                 vlib/genlib/clkdivce
 
--                 vlib/genlib/clkdivce
 
--                 bplib/bpgen/bp_rs232_2l4l_iob
 
--                 bplib/bpgen/bp_rs232_2l4l_iob
 
--                 bplib/bpgen/sn_humanio_rbus
 
--                 bplib/bpgen/sn_humanio_rbus
 
--                 vlib/rlink/rlink_sp1c
 
--                 bplib/fx2rlink/rlink_sp1c_fx2
 
 
 
--                 bplib/fx2rlink/ioleds_sp1c_fx2
 
--                 vlib/rri/rb_sres_or_3
 
--                 vlib/rri/rb_sres_or_3
 
--                 w11a/pdp11_core_rbus
 
--                 w11a/pdp11_core_rbus
 
--                 w11a/pdp11_core
 
--                 w11a/pdp11_core
 
--                 w11a/pdp11_bram
 
--                 w11a/pdp11_bram
 
--                 vlib/nxcramlib/nx_cram_dummy
 
--                 vlib/nxcramlib/nx_cram_dummy
Line 38... Line 39... 
-- Target Devices: generic
 
-- Target Devices: generic
 
-- Tool versions:  xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.26-0.29
 
-- Tool versions:  xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.26-0.29
 
--
 
--
 
-- Synthesized (xst):
 
-- Synthesized (xst):
 
-- Date         Rev  ise         Target      flop lutl lutm slic t peri
 
-- Date         Rev  ise         Target      flop lutl lutm slic t peri
 
 
 
-- 2013-04-20   509 13.3    O76d xc3s1200e-4 1541 4598  334 2889 ok: now + FX2 !
 
-- 2011-12-18   440 13.1    O40d xc3s1200e-4 1450 4439  270 2740 ok: LP+PC+DL+II
 
-- 2011-12-18   440 13.1    O40d xc3s1200e-4 1450 4439  270 2740 ok: LP+PC+DL+II
 
-- 2011-11-18   427 13.1    O40d xc3s1200e-4 1433 4374  242 2680 ok: LP+PC+DL+II
 
-- 2011-11-18   427 13.1    O40d xc3s1200e-4 1433 4374  242 2680 ok: LP+PC+DL+II
 
-- 2010-12-30   351 12.1    M53d xc3s1200e-4 1389 4368  242 2674 ok: LP+PC+DL+II
 
-- 2010-12-30   351 12.1    M53d xc3s1200e-4 1389 4368  242 2674 ok: LP+PC+DL+II
 
-- 2010-11-06   336 12.1    M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
 
-- 2010-11-06   336 12.1    M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
 
-- 2010-10-24   335 12.1    M53d xc3s1200e-4 1357 4546  242 2618 ok: LP+PC+DL+II
 
-- 2010-10-24   335 12.1    M53d xc3s1200e-4 1357 4546  242 2618 ok: LP+PC+DL+II
Line 62... Line 64... 
-- 2010-05-26   296 11.4    L68  xc3s1200e-4 1284 4079  224 2492 ok: LP+PC+DL+II
 
-- 2010-05-26   296 11.4    L68  xc3s1200e-4 1284 4079  224 2492 ok: LP+PC+DL+II
 
--   Note: till 2010-10-24 lutm included 'route-thru', after only logic
 
--   Note: till 2010-10-24 lutm included 'route-thru', after only logic
 
--
 
--
 
-- Revision History: 
-- Revision History: 
-- Date         Rev Version  Comment
 
-- Date         Rev Version  Comment
 
 
 
-- 2013-04-20   509   1.4    added fx2 (cuff) support; ATOWIDTH=7
 
-- 2011-12-23   444   1.3    remove clksys output hack
 
-- 2011-12-23   444   1.3    remove clksys output hack
 
-- 2011-12-18   440   1.2.7  use rlink_sp1c
 
-- 2011-12-18   440   1.2.7  use rlink_sp1c
 
-- 2011-11-26   433   1.2.6  use nx_cram_(dummy|memctl_as) now
 
-- 2011-11-26   433   1.2.6  use nx_cram_(dummy|memctl_as) now
 
-- 2011-11-23   432   1.2.5  update O_FLA_CE_N usage
 
-- 2011-11-23   432   1.2.5  update O_FLA_CE_N usage
 
-- 2011-11-19   427   1.2.4  now numeric_std clean
 
-- 2011-11-19   427   1.2.4  now numeric_std clean
Line 90... Line 93... 
-- 2010-05-30   297   1.0.1  put MEM_ACT_(R|W) on LED 6,7
 
-- 2010-05-30   297   1.0.1  put MEM_ACT_(R|W) on LED 6,7
 
-- 2010-05-28   295   1.0    Initial version (derived from sys_w11a_s3)
 
-- 2010-05-28   295   1.0    Initial version (derived from sys_w11a_s3)
 
------------------------------------------------------------------------------
 
------------------------------------------------------------------------------
 
--
 
--
 
-- w11a test design for nexys2
 
-- w11a test design for nexys2
 
--    w11a + rlink + serport
 
--    w11a + rlink + serport + cuff
 
--
 
--
 
-- Usage of Nexys 2 Switches, Buttons, LEDs:
 
-- Usage of Nexys 2 Switches, Buttons, LEDs:
 
--
 
--
 
--    SWI(7:2): no function (only connected to sn_humanio_rbus)
 
--    SWI(7:3): no function (only connected to sn_humanio_rbus)
 
--    SWI(1):   1 enable XON
 
--       (2)    0 -> int/ext RS242 port for rlink
 
--    SWI(0):   0 -> main board RS232 port
 
--              1 -> use USB interface for rlink
 
 
 
--       (1):   1 enable XON
 
 
 
--       (0):   0 -> main board RS232 port
 
--              1 -> Pmod B/top RS232 port
 
--              1 -> Pmod B/top RS232 port
 
--    
--    
--    LED(7)    MEM_ACT_W
 
--    LED(7)    MEM_ACT_W
 
--       (6)    MEM_ACT_R
 
--       (6)    MEM_ACT_R
 
--       (5)    cmdbusy (all rlink access, mostly rdma)
 
--       (5)    cmdbusy (all rlink access, mostly rdma)
Line 112... Line 117... 
--                  (0) user mode
 
--                  (0) user mode
 
--              if cpugo=0 shows cpurust
 
--              if cpugo=0 shows cpurust
 
--                (3:0) cpurust code
 
--                (3:0) cpurust code
 
--                  (4) '1'
 
--                  (4) '1'
 
--
 
--
 
--    DP(3):    not SER_MONI.txok       (shows tx back preasure)
 
--    DP(3:0) shows IO activity
 
--    DP(2):    SER_MONI.txact          (shows tx activity)
 
--            if SWI(2)=0 (serport)
 
--    DP(1):    not SER_MONI.rxok       (shows rx back preasure)
 
--                  (3):    not SER_MONI.txok       (shows tx back preasure)
 
--    DP(0):    SER_MONI.rxact          (shows rx activity)
 
--                  (2):    SER_MONI.txact          (shows tx activity)
 
 
 
--                  (1):    not SER_MONI.rxok       (shows rx back preasure)
 
 
 
--                  (0):    SER_MONI.rxact          (shows rx activity)
 
 
 
--            if SWI(2)=1 (fx2-usb)
 
 
 
--                  (3):    RB_SRES.busy            (shows rbus back preasure)
 
 
 
--                  (2):    RLB_TXBUSY              (shows tx back preasure)
 
 
 
--                  (1):    RLB_TXENA               (shows tx activity)
 
 
 
--                  (0):    RLB_RXVAL               (shows rx activity)
 
--
 
--
 
 
 
 
 
library ieee;
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_1164.all;
 
use ieee.numeric_std.all;
 
use ieee.numeric_std.all;
Line 128... Line 140... 
use work.xlib.all;
 
use work.xlib.all;
 
use work.genlib.all;
 
use work.genlib.all;
 
use work.serportlib.all;
 
use work.serportlib.all;
 
use work.rblib.all;
 
use work.rblib.all;
 
use work.rlinklib.all;
 
use work.rlinklib.all;
 
 
 
use work.fx2lib.all;
 
 
 
use work.fx2rlinklib.all;
 
use work.bpgenlib.all;
 
use work.bpgenlib.all;
 
use work.bpgenrbuslib.all;
 
use work.bpgenrbuslib.all;
 
use work.nxcramlib.all;
 
use work.nxcramlib.all;
 
use work.iblib.all;
 
use work.iblib.all;
 
use work.ibdlib.all;
 
use work.ibdlib.all;
Line 139... Line 153... 
use work.sys_conf.all;
 
use work.sys_conf.all;
 
 
 
 
 
-- ----------------------------------------------------------------------------
 
-- ----------------------------------------------------------------------------
 
 
 
 
 
entity sys_w11a_n2 is                   -- top level
 
entity sys_w11a_n2 is                   -- top level
 
                                        -- implements nexys2_fusp_aif
 
                                        -- implements nexys2_fusp_cuff_aif
 
  port (
 
  port (
 
    I_CLK50 : in slbit;                 -- 50 MHz clock
 
    I_CLK50 : in slbit;                 -- 50 MHz clock
 
    I_RXD : in slbit;                   -- receive data (board view)
 
    I_RXD : in slbit;                   -- receive data (board view)
 
    O_TXD : out slbit;                  -- transmit data (board view)
 
    O_TXD : out slbit;                  -- transmit data (board view)
 
    I_SWI : in slv8;                    -- n2 switches
 
    I_SWI : in slv8;                    -- n2 switches
Line 163... Line 177... 
    IO_MEM_DATA : inout slv16;          -- cram: data lines
 
    IO_MEM_DATA : inout slv16;          -- cram: data lines
 
    O_FLA_CE_N : out slbit;             -- flash ce..          (act.low)
 
    O_FLA_CE_N : out slbit;             -- flash ce..          (act.low)
 
    O_FUSP_RTS_N : out slbit;           -- fusp: rs232 rts_n
 
    O_FUSP_RTS_N : out slbit;           -- fusp: rs232 rts_n
 
    I_FUSP_CTS_N : in slbit;            -- fusp: rs232 cts_n
 
    I_FUSP_CTS_N : in slbit;            -- fusp: rs232 cts_n
 
    I_FUSP_RXD : in slbit;              -- fusp: rs232 rx
 
    I_FUSP_RXD : in slbit;              -- fusp: rs232 rx
 
    O_FUSP_TXD : out slbit              -- fusp: rs232 tx
 
    O_FUSP_TXD : out slbit;             -- fusp: rs232 tx
 
 
 
    I_FX2_IFCLK : in slbit;             -- fx2: interface clock
 
 
 
    O_FX2_FIFO : out slv2;              -- fx2: fifo address
 
 
 
    I_FX2_FLAG : in slv4;               -- fx2: fifo flags
 
 
 
    O_FX2_SLRD_N : out slbit;           -- fx2: read enable    (act.low)
 
 
 
    O_FX2_SLWR_N : out slbit;           -- fx2: write enable   (act.low)
 
 
 
    O_FX2_SLOE_N : out slbit;           -- fx2: output enable  (act.low)
 
 
 
    O_FX2_PKTEND_N : out slbit;         -- fx2: packet end     (act.low)
 
 
 
    IO_FX2_DATA : inout slv8            -- fx2: data lines
 
  );
 
  );
 
end sys_w11a_n2;
 
end sys_w11a_n2;
 
 
 
 
 
architecture syn of sys_w11a_n2 is
 
architecture syn of sys_w11a_n2 is
 
 
 
 
Line 185... Line 207... 
  signal DSP_DP  : slv4  := (others=>'0');
 
  signal DSP_DP  : slv4  := (others=>'0');
 
 
 
 
 
  signal RB_LAM  : slv16 := (others=>'0');
 
  signal RB_LAM  : slv16 := (others=>'0');
 
  signal RB_STAT : slv3  := (others=>'0');
 
  signal RB_STAT : slv3  := (others=>'0');
 
 
 
 
 
 
 
  signal RLB_MONI : rlb_moni_type := rlb_moni_init;
 
  signal SER_MONI : serport_moni_type := serport_moni_init;
 
  signal SER_MONI : serport_moni_type := serport_moni_init;
 
 
 
  signal FX2_MONI : fx2ctl_moni_type  := fx2ctl_moni_init;
 
 
 
 
 
  signal RB_MREQ     : rb_mreq_type := rb_mreq_init;
 
  signal RB_MREQ     : rb_mreq_type := rb_mreq_init;
 
  signal RB_SRES     : rb_sres_type := rb_sres_init;
 
  signal RB_SRES     : rb_sres_type := rb_sres_init;
 
  signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
 
  signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
 
  signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
 
  signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
Line 314... Line 338... 
      O_LED   => O_LED,
 
      O_LED   => O_LED,
 
      O_ANO_N => O_ANO_N,
 
      O_ANO_N => O_ANO_N,
 
      O_SEG_N => O_SEG_N
 
      O_SEG_N => O_SEG_N
 
    );
 
    );
 
 
 
 
 
  RLINK : rlink_sp1c
 
  RLINK : rlink_sp1c_fx2
 
    generic map (
 
    generic map (
 
      ATOWIDTH     => 6,                --  64 cycles access timeout
 
      ATOWIDTH     => 7,                -- 128 cycles access timeout
 
      ITOWIDTH     => 6,                --  64 periods max idle timeout
 
      ITOWIDTH     => 6,                --  64 periods max idle timeout
 
      CPREF        => c_rlink_cpref,
 
      CPREF        => c_rlink_cpref,
 
      IFAWIDTH     => 5,                --  32 word input fifo
 
      IFAWIDTH     => 5,                --  32 word input fifo
 
      OFAWIDTH     => 5,                --  32 word output fifo
 
      OFAWIDTH     => 5,                --  32 word output fifo
 
 
 
      PETOWIDTH    => sys_conf_fx2_petowidth,
 
 
 
      CCWIDTH      => sys_conf_fx2_ccwidth,
 
      ENAPIN_RLMON => sbcntl_sbf_rlmon,
 
      ENAPIN_RLMON => sbcntl_sbf_rlmon,
 
      ENAPIN_RBMON => sbcntl_sbf_rbmon,
 
      ENAPIN_RBMON => sbcntl_sbf_rbmon,
 
      CDWIDTH      => 13,
 
      CDWIDTH      => 13,
 
      CDINIT       => sys_conf_ser2rri_cdinit)
 
      CDINIT       => sys_conf_ser2rri_cdinit)
 
    port map (
 
    port map (
Line 333... Line 359... 
      CE_MSEC  => CE_MSEC,
 
      CE_MSEC  => CE_MSEC,
 
      CE_INT   => CE_MSEC,
 
      CE_INT   => CE_MSEC,
 
      RESET    => RESET,
 
      RESET    => RESET,
 
      ENAXON   => SWI(1),
 
      ENAXON   => SWI(1),
 
      ENAESC   => SWI(1),
 
      ENAESC   => SWI(1),
 
 
 
      ENAFX2   => SWI(2),
 
      RXSD     => RXD,
 
      RXSD     => RXD,
 
      TXSD     => TXD,
 
      TXSD     => TXD,
 
      CTS_N    => CTS_N,
 
      CTS_N    => CTS_N,
 
      RTS_N    => RTS_N,
 
      RTS_N    => RTS_N,
 
      RB_MREQ  => RB_MREQ,
 
      RB_MREQ  => RB_MREQ,
 
      RB_SRES  => RB_SRES,
 
      RB_SRES  => RB_SRES,
 
      RB_LAM   => RB_LAM,
 
      RB_LAM   => RB_LAM,
 
      RB_STAT  => RB_STAT,
 
      RB_STAT  => RB_STAT,
 
      RL_MONI  => open,
 
      RL_MONI  => open,
 
      SER_MONI => SER_MONI
 
      RLB_MONI => RLB_MONI,
 
 
 
      SER_MONI => SER_MONI,
 
 
 
      FX2_MONI => FX2_MONI,
 
 
 
      I_FX2_IFCLK    => I_FX2_IFCLK,
 
 
 
      O_FX2_FIFO     => O_FX2_FIFO,
 
 
 
      I_FX2_FLAG     => I_FX2_FLAG,
 
 
 
      O_FX2_SLRD_N   => O_FX2_SLRD_N,
 
 
 
      O_FX2_SLWR_N   => O_FX2_SLWR_N,
 
 
 
      O_FX2_SLOE_N   => O_FX2_SLOE_N,
 
 
 
      O_FX2_PKTEND_N => O_FX2_PKTEND_N,
 
 
 
      IO_FX2_DATA    => IO_FX2_DATA
 
    );
 
    );
 
 
 
 
 
  RB_SRES_OR : rb_sres_or_3
 
  RB_SRES_OR : rb_sres_or_3
 
    port map (
 
    port map (
 
      RB_SRES_1  => RB_SRES_CPU,
 
      RB_SRES_1  => RB_SRES_CPU,
Line 555... Line 592... 
        EI_VECT  => EI_VECT,
 
        EI_VECT  => EI_VECT,
 
        DISPREG  => DISPREG
 
        DISPREG  => DISPREG
 
      );
 
      );
 
  end generate IBD_MAXI;
 
  end generate IBD_MAXI;
 
 
 
 
 
  DSP_DAT(15 downto 0) <= DISPREG;
 
  IOLEDS : ioleds_sp1c_fx2
 
 
 
    port map (
 
 
 
      CLK      => CLK,
 
 
 
      CE_USEC  => CE_USEC,
 
 
 
      RESET    => CPU_RESET,
 
 
 
      ENAFX2   => SWI(2),
 
 
 
      RB_SRES  => RB_SRES,
 
 
 
      RLB_MONI => RLB_MONI,
 
 
 
      SER_MONI => SER_MONI,
 
 
 
      IOLEDS   => DSP_DP
 
 
 
    );
 
 
 
 
 
  DSP_DP(3) <= not SER_MONI.txok;
 
  DSP_DAT(15 downto 0) <= DISPREG;
 
  DSP_DP(2) <= SER_MONI.txact;
 
 
 
  DSP_DP(1) <= not SER_MONI.rxok;
 
 
 
  DSP_DP(0) <= SER_MONI.rxact;
 
 
 
 
 
 
 
  proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
 
  proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
 
    variable iled : slv8 := (others=>'0');
 
    variable iled : slv8 := (others=>'0');
 
  begin
 
  begin
 
    iled := (others=>'0');
 
    iled := (others=>'0');

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