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-- $Id: sys_w11a_n2.vhd 341 2010-11-27 23:05:43Z mueller $
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-- $Id: sys_w11a_n2.vhd 351 2010-12-30 21:50:54Z mueller $
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--
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Description: w11a test design for nexys2
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-- Description: w11a test design for nexys2
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--
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--
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-- Dependencies: vlib/xlib/dcm_sp_sfs
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-- Dependencies: vlib/xlib/dcm_sp_sfs
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-- vlib/genlib/clkdivce
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-- vlib/genlib/clkdivce
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-- bplib/s3board/s3_rs232_iob_int_ext
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-- bplib/s3board/s3_rs232_iob_int_ext
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-- bplib/s3board/s3_humanio_rri
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-- bplib/s3board/s3_humanio_rbus
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-- vlib/rri/rri_core_serport
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-- vlib/rlink/rlink_base_serport
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-- vlib/rri/rb_sres_or_3
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-- vlib/rri/rb_sres_or_3
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-- w11a/pdp11_core_rri
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-- w11a/pdp11_core_rbus
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-- w11a/pdp11_core
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-- w11a/pdp11_core
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-- w11a/pdp11_bram
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-- w11a/pdp11_bram
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-- vlib/nexys2/n2_cram_dummy
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-- vlib/nexys2/n2_cram_dummy
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-- w11a/pdp11_cache
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-- w11a/pdp11_cache
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-- w11a/pdp11_mem70
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-- w11a/pdp11_mem70
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.26-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.26-0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II
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-- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
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-- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
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-- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II
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-- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II
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-- 2010-10-17 333 12.1 M53d xc3s1200e-4 1350 4541 242 2617 ok: LP+PC+DL+II
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-- 2010-10-17 333 12.1 M53d xc3s1200e-4 1350 4541 242 2617 ok: LP+PC+DL+II
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-- 2010-10-16 332 12.1 M53d xc3s1200e-4 1338 4545 242 2629 ok: LP+PC+DL+II
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-- 2010-10-16 332 12.1 M53d xc3s1200e-4 1338 4545 242 2629 ok: LP+PC+DL+II
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-- 2010-06-27 310 12.1 M53d xc3s1200e-4 1337 4307 242 2630 ok: LP+PC+DL+II
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-- 2010-06-27 310 12.1 M53d xc3s1200e-4 1337 4307 242 2630 ok: LP+PC+DL+II
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-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II
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-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II
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-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
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-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-12-30 351 1.2 ported to rbv3
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-- 2010-11-27 341 1.1.8 add DCM; new sys_conf consts for mem and clkdiv
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-- 2010-11-27 341 1.1.8 add DCM; new sys_conf consts for mem and clkdiv
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-- 2010-11-13 338 1.1.7 add O_CLKSYS (for DCM derived system clock)
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-- 2010-11-13 338 1.1.7 add O_CLKSYS (for DCM derived system clock)
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-- 2010-11-06 336 1.1.6 rename input pin CLK -> I_CLK50
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-- 2010-11-06 336 1.1.6 rename input pin CLK -> I_CLK50
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-- 2010-10-23 335 1.1.5 rename RRI_LAM->RB_LAM;
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-- 2010-10-23 335 1.1.5 rename RRI_LAM->RB_LAM;
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-- 2010-06-26 309 1.1.4 use constants for rbus addresses (rbaddr_...)
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-- 2010-06-26 309 1.1.4 use constants for rbus addresses (rbaddr_...)
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-- 2010-05-30 297 1.0.1 put MEM_ACT_(R|W) on LED 6,7
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-- 2010-05-30 297 1.0.1 put MEM_ACT_(R|W) on LED 6,7
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-- 2010-05-28 295 1.0 Initial version (derived from sys_w11a_s3)
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-- 2010-05-28 295 1.0 Initial version (derived from sys_w11a_s3)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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-- w11a test design for nexys2
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-- w11a test design for nexys2
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-- w11a + rri + serport
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-- w11a + rlink + serport
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--
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--
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-- Usage of Nexys 2 Switches, Buttons, LEDs:
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-- Usage of Nexys 2 Switches, Buttons, LEDs:
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--
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--
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-- SWI(0): 0 -> main board RS232 port
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-- SWI(0): 0 -> main board RS232 port
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-- 1 -> Pmod B/top RS232 port
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-- 1 -> Pmod B/top RS232 port
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-- (3) kernel mode, pri=0
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-- (3) kernel mode, pri=0
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-- (4) kernel mode, pri>0
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-- (4) kernel mode, pri>0
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-- if cpugo=0 shows cpurust
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-- if cpugo=0 shows cpurust
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-- (3:0) cpurust code
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-- (3:0) cpurust code
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-- (4) '1'
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-- (4) '1'
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-- (5) cmdbusy (all rri access, mostly rdma)
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-- (5) cmdbusy (all rlink access, mostly rdma)
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-- (6) MEM_ACT_R
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-- (6) MEM_ACT_R
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-- (7) MEM_ACT_W
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-- (7) MEM_ACT_W
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--
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--
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-- DP(0): RXSD (inverted to signal activity)
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-- DP(0): RXSD (inverted to signal activity)
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-- DP(1): RTS_N (shows rx back preasure)
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-- DP(1): RTS_N (shows rx back preasure)
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.xlib.all;
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use work.xlib.all;
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use work.genlib.all;
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use work.genlib.all;
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use work.rrilib.all;
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use work.rblib.all;
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use work.rlinklib.all;
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use work.s3boardlib.all;
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use work.s3boardlib.all;
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use work.nexys2lib.all;
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use work.nexys2lib.all;
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use work.iblib.all;
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use work.iblib.all;
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use work.ibdlib.all;
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use work.ibdlib.all;
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use work.pdp11.all;
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use work.pdp11.all;
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O_TXD1 => O_FUSP_TXD,
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O_TXD1 => O_FUSP_TXD,
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I_CTS1_N => I_FUSP_CTS_N,
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I_CTS1_N => I_FUSP_CTS_N,
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O_RTS1_N => O_FUSP_RTS_N
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O_RTS1_N => O_FUSP_RTS_N
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);
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);
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HIO : s3_humanio_rri
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HIO : s3_humanio_rbus
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generic map (
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generic map (
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DEBOUNCE => sys_conf_hio_debounce,
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DEBOUNCE => sys_conf_hio_debounce,
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RB_ADDR => rbaddr_hio)
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RB_ADDR => rbaddr_hio)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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| Line 296... |
Line 299... |
O_LED => O_LED,
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O_LED => O_LED,
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O_ANO_N => O_ANO_N,
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O_ANO_N => O_ANO_N,
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O_SEG_N => O_SEG_N
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O_SEG_N => O_SEG_N
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);
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);
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RRI : rri_core_serport
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RLINK : rlink_base_serport
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generic map (
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generic map (
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ATOWIDTH => 6, -- 64 cycles access timeout
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ATOWIDTH => 6, -- 64 cycles access timeout
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ITOWIDTH => 6, -- 64 periods max idle timeout
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ITOWIDTH => 6, -- 64 periods max idle timeout
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IFAWIDTH => 5, -- 32 word input fifo
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OFAWIDTH => 0, -- no output fifo
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CDWIDTH => 13,
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CDWIDTH => 13,
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CDINIT => sys_conf_ser2rri_cdinit)
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CDINIT => sys_conf_ser2rri_cdinit)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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| Line 315... |
Line 320... |
CTS_N => CTS_N,
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CTS_N => CTS_N,
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RTS_N => RTS_N,
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RTS_N => RTS_N,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES,
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RB_SRES => RB_SRES,
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RB_LAM => RB_LAM,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT
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RB_STAT => RB_STAT,
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RL_MONI => open,
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RL_SER_MONI => open
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);
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);
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RB_SRES_OR : rb_sres_or_3
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RB_SRES_OR : rb_sres_or_3
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port map (
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port map (
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RB_SRES_1 => RB_SRES_CPU,
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RB_SRES_1 => RB_SRES_CPU,
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RB_SRES_2 => RB_SRES_IBD,
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RB_SRES_2 => RB_SRES_IBD,
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RB_SRES_3 => RB_SRES_HIO,
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RB_SRES_3 => RB_SRES_HIO,
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RB_SRES_OR => RB_SRES
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RB_SRES_OR => RB_SRES
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);
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);
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RB2CP : pdp11_core_rri
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RB2CP : pdp11_core_rbus
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generic map (
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generic map (
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RB_ADDR_CORE => rbaddr_core0,
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RB_ADDR_CORE => rbaddr_core0,
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RB_ADDR_IBUS => rbaddr_ibus)
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RB_ADDR_IBUS => rbaddr_ibus)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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