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-- $Id: clkdivce.vhd 341 2010-11-27 23:05:43Z mueller $
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-- $Id: clkdivce.vhd 418 2011-10-23 20:11:40Z mueller $
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--
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--
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-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Description: Generate usec and msec enable signals
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-- Description: Generate usec and msec enable signals
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-10-22 418 1.0.3 now numeric_std clean
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-- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port
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-- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-30 62 1.0 Initial version
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-- 2007-06-30 62 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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entity clkdivce is -- generate usec/msec ce pulses
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entity clkdivce is -- generate usec/msec ce pulses
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generic (
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generic (
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usec : slbit; -- usec pulse
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usec : slbit; -- usec pulse
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msec : slbit; -- msec pulse
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msec : slbit; -- msec pulse
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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conv_std_logic_vector(USECDIV-1,CDUWIDTH),
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slv(to_unsigned(USECDIV-1,CDUWIDTH)),
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conv_std_logic_vector(MSECDIV-1,10),
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slv(to_unsigned(MSECDIV-1,10)),
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'0','0'
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'0','0'
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);
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal N_REGS : regs_type := regs_init; -- next value state regs
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severity FAILURE;
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severity FAILURE;
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if CLK'event and CLK='1' then
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if rising_edge(CLK) then
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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end process proc_regs;
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n := R_REGS;
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n := R_REGS;
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n.usec := '0';
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n.usec := '0';
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n.msec := '0';
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n.msec := '0';
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n.ucnt := unsigned(r.ucnt) - 1;
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n.ucnt := slv(unsigned(r.ucnt) - 1);
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if unsigned(r.ucnt) = 0 then
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if unsigned(r.ucnt) = 0 then
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n.usec := '1';
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n.usec := '1';
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n.ucnt := conv_std_logic_vector(USECDIV-1,CDUWIDTH);
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n.ucnt := slv(to_unsigned(USECDIV-1,CDUWIDTH));
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n.mcnt := unsigned(r.mcnt) - 1;
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n.mcnt := slv(unsigned(r.mcnt) - 1);
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if unsigned(r.mcnt) = 0 then
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if unsigned(r.mcnt) = 0 then
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n.msec := '1';
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n.msec := '1';
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n.mcnt := conv_std_logic_vector(MSECDIV-1,10);
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n.mcnt := slv(to_unsigned(MSECDIV-1,10));
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end if;
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end if;
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end if;
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end if;
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N_REGS <= n;
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N_REGS <= n;
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