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-- $Id: clkdivce.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: clkdivce.vhd 341 2010-11-27 23:05:43Z mueller $
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--
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--
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Description: Generate usec and msec enable signals
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-- Description: Generate usec and msec enable signals
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port
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-- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-30 62 1.0 Initial version
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-- 2007-06-30 62 1.0 Initial version
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