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-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $
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--
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--
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-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Direct instantiation of Xilinx UNISIM primitives
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-- Direct instantiation of Xilinx UNISIM primitives
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: Spartan-3, Virtex-2,-4
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-- Target Devices: Spartan-3, Virtex-2,-4
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-08-14 406 1.0.2 cleaner code for L_DI initialization
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-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
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-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
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-- 2008-03-08 123 1.0 Initial version
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-- 2008-03-08 123 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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constant dw_mem : positive := ((DWIDTH+35)/36)*36;
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constant dw_mem : positive := ((DWIDTH+35)/36)*36;
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signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
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begin
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begin
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DI_PAD: if dw_mem>DWIDTH generate
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L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
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end generate DI_PAD;
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L_DI(DI'range) <= DI;
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L_DI(DI'range) <= DI;
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GL: for i in dw_mem/36-1 downto 0 generate
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GL: for i in dw_mem/36-1 downto 0 generate
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MEM : RAMB16_S36
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MEM : RAMB16_S36
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generic map (
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generic map (
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constant dw_mem : positive := ((DWIDTH+17)/18)*18;
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constant dw_mem : positive := ((DWIDTH+17)/18)*18;
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signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
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begin
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begin
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DI_PAD: if dw_mem>DWIDTH generate
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L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
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end generate DI_PAD;
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L_DI(DI'range) <= DI;
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L_DI(DI'range) <= DI;
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GL: for i in dw_mem/18-1 downto 0 generate
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GL: for i in dw_mem/18-1 downto 0 generate
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MEM : RAMB16_S18
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MEM : RAMB16_S18
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generic map (
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generic map (
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constant dw_mem : positive := ((DWIDTH+8)/9)*9;
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constant dw_mem : positive := ((DWIDTH+8)/9)*9;
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signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
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begin
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begin
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DI_PAD: if dw_mem>DWIDTH generate
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L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
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end generate DI_PAD;
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L_DI(DI'range) <= DI;
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L_DI(DI'range) <= DI;
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GL: for i in dw_mem/9-1 downto 0 generate
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GL: for i in dw_mem/9-1 downto 0 generate
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MEM : RAMB16_S9
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MEM : RAMB16_S9
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generic map (
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generic map (
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constant dw_mem : positive := ((DWIDTH+3)/4)*4;
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constant dw_mem : positive := ((DWIDTH+3)/4)*4;
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signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
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begin
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begin
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DI_PAD: if dw_mem>DWIDTH generate
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L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
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end generate DI_PAD;
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L_DI(DI'range) <= DI;
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L_DI(DI'range) <= DI;
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GL: for i in dw_mem/4-1 downto 0 generate
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GL: for i in dw_mem/4-1 downto 0 generate
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MEM : RAMB16_S4
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MEM : RAMB16_S4
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generic map (
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generic map (
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constant dw_mem : positive := ((DWIDTH+1)/2)*2;
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constant dw_mem : positive := ((DWIDTH+1)/2)*2;
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signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
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signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
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begin
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begin
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DI_PAD: if dw_mem>DWIDTH generate
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L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
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end generate DI_PAD;
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L_DI(DI'range) <= DI;
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L_DI(DI'range) <= DI;
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GL: for i in dw_mem/2-1 downto 0 generate
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GL: for i in dw_mem/2-1 downto 0 generate
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MEM : RAMB16_S2
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MEM : RAMB16_S2
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generic map (
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generic map (
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