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-- $Id: rb_mon_sb.vhd 346 2010-12-22 22:59:26Z mueller $
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-- $Id: rb_mon_sb.vhd 444 2011-12-25 10:04:58Z mueller $
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--
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: rb_mon_sb - sim
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-- Module Name: rb_mon_sb - sim
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-- Description: simbus wrapper for rbus monitor (for tb's)
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-- Description: simbus wrapper for rbus monitor (for tb's)
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--
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--
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-- Dependencies: simbus
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-- Dependencies: simbus
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-- simlib/simclkcnt
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-- rb_mon
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-- Test bench: -
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-- Test bench: -
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-12-23 444 3.1 use simclkcnt instead of simbus global
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-- 2010-12-22 346 3.0 renamed rritb_rbmon_sb -> rb_mon_sb
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-- 2010-12-22 346 3.0 renamed rritb_rbmon_sb -> rb_mon_sb
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-- 2010-06-05 301 2.0.2 renamed _rpmon -> _rbmon
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-- 2010-06-05 301 2.0.2 renamed _rpmon -> _rbmon
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-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
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-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
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-- drop RP_IINT signal from interfaces
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-- drop RP_IINT signal from interfaces
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-- use sbcntl_sbf_cpmon def
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-- use sbcntl_sbf_cpmon def
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architecture sim of rb_mon_sb is
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architecture sim of rb_mon_sb is
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signal ENA : slbit := '0';
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signal ENA : slbit := '0';
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signal CLK_CYCLE : integer := 0;
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begin
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begin
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assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
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assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
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report "assert(ENAPIN in SB_CNTL'range)" severity failure;
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report "assert(ENAPIN in SB_CNTL'range)" severity failure;
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CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
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ENA <= to_x01(SB_CNTL(ENAPIN));
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ENA <= to_x01(SB_CNTL(ENAPIN));
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RBMON : rb_mon
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RBMON : rb_mon
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generic map (
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generic map (
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DBASE => DBASE)
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DBASE => DBASE)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CLK_CYCLE => SB_CLKCYCLE,
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CLK_CYCLE => CLK_CYCLE,
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ENA => ENA,
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ENA => ENA,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES,
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RB_SRES => RB_SRES,
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RB_LAM => RB_LAM,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT
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RB_STAT => RB_STAT
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