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-- $Id: rri_core.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: rlink_core.vhd 350 2010-12-28 16:40:11Z mueller $
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--
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: rri_core - syn
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-- Module Name: rlink_core - syn
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-- Description: rri: core interface
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-- Description: rlink core with 9bit interface
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--
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--
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-- Dependencies: comlib/crc8
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-- Dependencies: comlib/crc8
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--
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--
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-- Test bench: tb/tb_rri_core
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-- Test bench: tb/tb_rlink_direct
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-- tb/tb_rritba_ttcombo
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-- tb/tb_rlink_serport
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-- tb/tb_rriext_ttcombo
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-- tb/tb_rlink_tba_ttcombo
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-12-04 343 12.1 M53d xc3s1000-4 155 322 0 199 s 8.9
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-- 2010-06-06 302 11.4 L68 xc3s1000-4 151 323 0 197 s 8.9
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-- 2010-06-06 302 11.4 L68 xc3s1000-4 151 323 0 197 s 8.9
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-- 2010-04-03 274 11.4 L68 xc3s1000-4 148 313 0 190 s 8.0
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-- 2010-04-03 274 11.4 L68 xc3s1000-4 148 313 0 190 s 8.0
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-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 147 321 0 197 s 8.3
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-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 147 321 0 197 s 8.3
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
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-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
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-- 2010-12-22 346 3.1 wblk dcrc error: send nak, transit to s_error now;
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-- rename stat flags: [cd]crc->[cd]err, ioto->rbnak,
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-- ioerr->rberr; '111' cmd now aborts via s_txnak and
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-- sets cerr flag; set [cd]err on eop/nak aborts;
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-- 2010-12-04 343 3.0 renamed rri_ -> rlink_; rbus V3 interface: use now
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-- aval,re,we; add new states: s_rstart, s_wstart
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-- 2010-06-20 308 2.6 use rbinit,rbreq,rbwe state flops to drive rb_mreq;
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-- 2010-06-20 308 2.6 use rbinit,rbreq,rbwe state flops to drive rb_mreq;
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-- now nak on reserved cmd 111; use do_comma_abort();
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-- now nak on reserved cmd 111; use do_comma_abort();
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-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
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-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
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-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
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-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
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-- 2010-06-03 299 2.1.2 drop unneeded unsigned casts; change init encoding
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-- 2010-06-03 299 2.1.2 drop unneeded unsigned casts; change init encoding
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Line 79... |
Line 88... |
--
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--
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-- 000 read reg (rreg):
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-- 000 read reg (rreg):
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-- rx: cmd addr ccrc
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-- rx: cmd addr ccrc
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-- tx: cmd dl dh stat crc
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-- tx: cmd dl dh stat crc
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-- seq: _rxcmd _rxaddr _rxccrc (_txcmd|_txnak)
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-- seq: _rxcmd _rxaddr _rxccrc (_txcmd|_txnak)
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-- _rreg _txdatl _txdath _txstat _txcrc (_rxcmd|_idle)
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-- _rstart _rreg _txdatl _txdath _txstat _txcrc -> _rxcmd
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--
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--
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-- 001 read blk (rblk):
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-- 001 read blk (rblk):
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-- rx: cmd addr cnt ccrc
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-- rx: cmd addr cnt ccrc
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-- tx: cmd cnt dl dh ... stat crc
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-- tx: cmd cnt dl dh ... stat crc
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-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) _txcnt
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-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) _txcnt
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-- {_rreg _txdatl _txdath _blk}* _txstat _txcrc (_rxcmd|_idle)
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-- {_rstart _rreg _txdatl _txdath _blk}*
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-- _txstat _txcrc -> _rxcmd
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--
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--
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-- 010 write reg (wreg):
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-- 010 write reg (wreg):
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-- rx: cmd addr dl dh ccrc
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-- rx: cmd addr dl dh ccrc
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-- tx: cmd stat crc
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-- tx: cmd stat crc
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-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
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-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
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-- seq: _wreg _txstat _txcrc (_rxcmd|_idle)
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-- _wstart _wreg _txstat _txcrc -> _rxcmd
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--
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--
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-- 011 write blk (wblk):
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-- 011 write blk (wblk):
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-- rx: cmd addr cnt ccrc dl dh ... dcrc
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-- rx: cmd addr cnt ccrc dl dh ... dcrc
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-- tx: cmd stat crc
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-- tx: cmd stat crc
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-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak)
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-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak)
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-- {_rxdatl _rxdath _wreg _blk}* _rxdcrc _txstat _txcrc (_rxcmd|_idle)
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-- {_rxdatl _rxdath _wstart _wreg _blk}*
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-- _rxdcrc _txstat _txcrc -> (_rxcmd|_txnak)
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--
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--
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-- 100 read stat (stat):
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-- 100 read stat (stat):
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-- rx: cmd ccrc
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-- rx: cmd ccrc
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-- tx: cmd ccmd dl dh stat crc
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-- tx: cmd ccmd dl dh stat crc
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-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
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-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
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-- _txccmd _txdatl _txdath _txstat _txcrc (_rxcmd|_idle)
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-- _txccmd _txdatl _txdath _txstat _txcrc -> _rxcmd
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--
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--
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-- 101 read attn (attn):
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-- 101 read attn (attn):
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-- rx: cmd ccrc
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-- rx: cmd ccrc
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-- tx: cmd dl dh stat crc
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-- tx: cmd dl dh stat crc
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-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
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-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
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-- _attn _txdatl _txdath _txstat _txcrc (_rxcmd|_idle)
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-- _attn _txdatl _txdath _txstat _txcrc -> _rxcmd
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--
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--
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-- 110 write init (init):
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-- 110 write init (init):
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-- rx: cmd addr dl dh ccrc
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-- rx: cmd addr dl dh ccrc
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-- tx: cmd stat crc
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-- tx: cmd stat crc
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-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
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-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
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-- seq: _txstat _txcrc (_rxcmd|_idle)
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-- _txstat _txcrc -> _rxcmd
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-- like wreg, but no rp_we - rp_hold, just a 1 cycle rp_init pulse
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-- like wreg, but no rp_we - rp_hold, just a 1 cycle rp_init pulse
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--
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--
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-- 111 is currently not a legal command and causes a nak
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-- 111 is currently not a legal command and causes a nak
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-- seq: _txnak
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-- seq: _txnak
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--
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--
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-- The state bits nakcerr and nakderr determine whether cerr/derr is set
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-- when s_txnak is entered. cerr is '1' during command receive, derr is '1'
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-- during data wblk data receive phase:
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-- nakcerr set in s_rxcmd (when command received, unless it's stat)
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-- clr in s_txcmd (when wblk)
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-- clr in s_txnak
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-- clr in s_txcrc (for sucessful completion)
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-- nakderr set in s_txcmd (when wblk)
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-- clr in s_txnak
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-- clr in s_txcrc (for sucessful completion)
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--
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-- The different rbus cycle types are encoded as:
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-- The different rbus cycle types are encoded as:
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--
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--
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-- init ack we
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-- init aval re we
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-- 0 0 0 idle
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-- 0 0 0 0 idle
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-- 0 0 1 idle
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-- 0 0 1 0 not allowed
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-- 0 1 0 read
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-- 0 0 0 1 not allowed
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-- 0 1 1 write
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-- 0 1 1 0 read
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-- 1 0 0 internal init
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-- 0 1 0 1 write
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-- 1 0 1 external init
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-- 1 0 0 0 internal init
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-- 1 1 0 not allowed
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-- 1 0 0 1 external init
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-- 1 1 1 not allowed
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-- 1 0 1 0 not allowed
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-- * * 1 1 not allowed
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-- 1 1 * * not allowed
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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|
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.comlib.all;
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use work.comlib.all;
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use work.rrilib.all;
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use work.rblib.all;
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use work.rlinklib.all;
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entity rri_core is -- rri, core interface
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entity rlink_core is -- rlink core with 9bit interface
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generic (
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generic (
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ATOWIDTH : positive := 5; -- access timeout counter width
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ATOWIDTH : positive := 5; -- access timeout counter width
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ITOWIDTH : positive := 6); -- idle timeout counter width
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ITOWIDTH : positive := 6); -- idle timeout counter width
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_INT : in slbit := '0'; -- rri ito time unit clock enable
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CE_INT : in slbit := '0'; -- rri ito time unit clock enable
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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CP_DI : in slv9; -- comm port: data in
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RL_DI : in slv9; -- rlink 9b: data in
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CP_ENA : in slbit; -- comm port: data enable
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RL_ENA : in slbit; -- rlink 9b: data enable
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CP_BUSY : out slbit; -- comm port: data busy
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RL_BUSY : out slbit; -- rlink 9b: data busy
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CP_DO : out slv9; -- comm port: data out
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RL_DO : out slv9; -- rlink 9b: data out
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CP_VAL : out slbit; -- comm port: data valid
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RL_VAL : out slbit; -- rlink 9b: data valid
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CP_HOLD : in slbit; -- comm port: data hold
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RL_HOLD : in slbit; -- rlink 9b: data hold
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CP_FLUSH : out slbit; -- comm port: data flush
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RL_MONI : out rl_moni_type; -- rlink: monitor port
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16; -- rbus: look at me
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RB_LAM : in slv16; -- rbus: look at me
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RB_STAT : in slv3 -- rbus: status flags
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RB_STAT : in slv3 -- rbus: status flags
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);
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);
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end entity rri_core;
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end entity rlink_core;
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architecture syn of rri_core is
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architecture syn of rlink_core is
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|
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type state_type is (
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type state_type is (
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s_idle, -- s_idle: wait for sop
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s_idle, -- s_idle: wait for sop
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s_txito, -- s_txito: send timeout symbol
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s_txito, -- s_txito: send timeout symbol
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s_txsop, -- s_txsop: send sop
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s_txsop, -- s_txsop: send sop
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Line 182... |
Line 207... |
s_rxdath, -- s_rxdath: wait for data high
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s_rxdath, -- s_rxdath: wait for data high
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s_rxcnt, -- s_rxcnt: wait for count
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s_rxcnt, -- s_rxcnt: wait for count
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s_rxccrc, -- s_rxccrc: wait for command crc
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s_rxccrc, -- s_rxccrc: wait for command crc
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s_txcmd, -- s_txcmd: send cmd
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s_txcmd, -- s_txcmd: send cmd
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s_txcnt, -- s_txcnt: send cnt
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s_txcnt, -- s_txcnt: send cnt
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s_rreg, -- s_rreg: reg or blk read
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s_rstart, -- s_rstart: start reg or blk read
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s_rreg, -- s_rreg: do reg or blk read
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s_txdatl, -- s_txdatl: send data low
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s_txdatl, -- s_txdatl: send data low
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s_txdath, -- s_txdath: send data high
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s_txdath, -- s_txdath: send data high
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s_wreg, -- s_wreg: reg or blk write
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s_wstart, -- s_wstart: start reg or blk write
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s_wreg, -- s_wreg: do reg or blk write
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s_blk, -- s_blk: block count handling
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s_blk, -- s_blk: block count handling
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s_rxdcrc, -- s_rxdcrc: wait for data crc
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s_rxdcrc, -- s_rxdcrc: wait for data crc
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s_attn, -- s_attn: handle attention flags
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s_attn, -- s_attn: handle attention flags
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s_txccmd, -- s_txccmd: send last command
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s_txccmd, -- s_txccmd: send last command
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s_txstat, -- s_txstat: send status
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s_txstat, -- s_txstat: send status
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Line 211... |
Line 238... |
itocnt : slv(ITOWIDTH-1 downto 0); -- idle timeout counter
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itocnt : slv(ITOWIDTH-1 downto 0); -- idle timeout counter
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itoval : slv(ITOWIDTH-1 downto 0); -- idle timeout value
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itoval : slv(ITOWIDTH-1 downto 0); -- idle timeout value
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itoena : slbit; -- idle timeout enable flag
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itoena : slbit; -- idle timeout enable flag
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anena : slbit; -- attn notification enable flag
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anena : slbit; -- attn notification enable flag
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andone : slbit; -- attn notification done
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andone : slbit; -- attn notification done
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ccrc : slbit; -- stat: command crc error
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cerr : slbit; -- stat: command error
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dcrc : slbit; -- stat: data crc error
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derr : slbit; -- stat: data error
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ioto : slbit; -- stat: i/o time out
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rbnak: slbit; -- stat: rbus no ack or timeout
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ioerr : slbit; -- stat: i/o time error
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rberr : slbit; -- stat: rbus err bit set
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nakeop : slbit; -- send eop after nak
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nakeop : slbit; -- send eop after nak
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nakcerr : slbit; -- set cerr after nak
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nakderr : slbit; -- set derr after nak
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rbinit : slbit; -- rbus init signal
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rbinit : slbit; -- rbus init signal
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rbreq : slbit; -- rbus req signal
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rbaval : slbit; -- rbus aval signal
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rbre : slbit; -- rbus re signal
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rbwe : slbit; -- rbus we signal
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rbwe : slbit; -- rbus we signal
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flush : slbit; -- flush pulse
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moneop : slbit; -- rl_moni: eop send pulse
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monattn : slbit; -- rl_moni: attn send pulse
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monlamp : slbit; -- rl_moni: attn pending state
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stat : slv3; -- external status flags
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stat : slv3; -- external status flags
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end record regs_type;
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end record regs_type;
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|
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constant atocnt_init : slv(ATOWIDTH-1 downto 0) := (others=>'1');
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constant atocnt_init : slv(ATOWIDTH-1 downto 0) := (others=>'1');
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constant itocnt_init : slv(ITOWIDTH-1 downto 0) := (others=>'0');
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constant itocnt_init : slv(ITOWIDTH-1 downto 0) := (others=>'0');
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Line 249... |
Line 281... |
itocnt_init, -- itocnt
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itocnt_init, -- itocnt
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itocnt_init, -- itoval
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itocnt_init, -- itoval
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'0', -- itoena
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'0', -- itoena
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'0','0', -- anena, andone
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'0','0', -- anena, andone
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'0','0','0','0', -- stat flags
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'0','0','0','0', -- stat flags
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'0', -- nakeop
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'0','0','0', -- nakeop,nakcerr,nakderr
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'0','0','0', -- rbinit,rbreq,rbwe
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'0','0','0','0', -- rbinit,rbaval,rbre,rbwe
|
'0', -- flush
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'0','0','0', -- moneop,monattn,monlamp
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(others=>'0') -- stat
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(others=>'0') -- stat
|
);
|
);
|
|
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signal R_REGS : regs_type := regs_init; -- state registers
|
signal R_REGS : regs_type := regs_init; -- state registers
|
signal N_REGS : regs_type := regs_init; -- next value state regs
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signal N_REGS : regs_type := regs_init; -- next value state regs
|
Line 276... |
Line 308... |
ICRC : crc8 -- crc generator for input data
|
ICRC : crc8 -- crc generator for input data
|
port map (
|
port map (
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CLK => CLK,
|
CLK => CLK,
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RESET => CRC_RESET,
|
RESET => CRC_RESET,
|
ENA => ICRC_ENA,
|
ENA => ICRC_ENA,
|
DI => CP_DI(7 downto 0),
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DI => RL_DI(7 downto 0),
|
CRC => ICRC_OUT
|
CRC => ICRC_OUT
|
);
|
);
|
|
|
OCRC : crc8 -- crc generator for output data
|
OCRC : crc8 -- crc generator for output data
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port map (
|
port map (
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Line 302... |
Line 334... |
end if;
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end if;
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end if;
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end if;
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|
|
end process proc_regs;
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end process proc_regs;
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|
|
proc_next: process (R_REGS, CE_INT, CP_DI, CP_ENA, CP_HOLD, RB_LAM,
|
proc_next: process (R_REGS, CE_INT, RL_DI, RL_ENA, RL_HOLD, RB_LAM,
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RB_SRES, RB_STAT, ICRC_OUT, OCRC_OUT)
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RB_SRES, RB_STAT, ICRC_OUT, OCRC_OUT)
|
|
|
variable r : regs_type := regs_init;
|
variable r : regs_type := regs_init;
|
variable n : regs_type := regs_init;
|
variable n : regs_type := regs_init;
|
|
|
Line 319... |
Line 351... |
variable ito_end : slbit := '0';
|
variable ito_end : slbit := '0';
|
variable crcreset : slbit := '0';
|
variable crcreset : slbit := '0';
|
variable icrcena : slbit := '0';
|
variable icrcena : slbit := '0';
|
variable ocrcena : slbit := '0';
|
variable ocrcena : slbit := '0';
|
variable has_attn : slbit := '0';
|
variable has_attn : slbit := '0';
|
|
variable snd_attn : slbit := '0';
|
variable idi8 : slv8 := (others=>'0');
|
variable idi8 : slv8 := (others=>'0');
|
variable is_comma : slbit := '0';
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variable is_comma : slbit := '0';
|
variable comma_typ : slv4 := "0000";
|
variable comma_typ : slv4 := "0000";
|
|
|
procedure do_comma_abort(nstate : inout state_type;
|
procedure do_comma_abort(nstate : inout state_type;
|
Line 340... |
Line 373... |
begin
|
begin
|
|
|
r := R_REGS;
|
r := R_REGS;
|
n := R_REGS;
|
n := R_REGS;
|
|
|
idi8 := CP_DI(7 downto 0); -- get data part of CP_DI
|
idi8 := RL_DI(7 downto 0); -- get data part of RL_DI
|
is_comma := CP_DI(8); -- get comma marker
|
is_comma := RL_DI(8); -- get comma marker
|
comma_typ := CP_DI(3 downto 0); -- get comma type
|
comma_typ := RL_DI(3 downto 0); -- get comma type
|
|
|
n.rbinit := '0'; -- clear rbinit,rbreq,rbwe by default
|
n.rbinit := '0'; -- clear rb(init|aval|re|we) by default
|
n.rbreq := '0'; -- they must always be set by the
|
n.rbaval := '0'; -- they must always be set by the
|
n.rbwe := '0'; -- 'previous state'
|
n.rbre := '0'; -- 'previous state'
|
|
n.rbwe := '0'; --
|
n.flush := '0'; -- dito for flush
|
|
|
n.moneop := '0'; -- default '0', only set by states
|
|
n.monattn := '0'; -- "
|
|
n.monlamp := '0'; --
|
|
|
ibusy := '1'; -- default is to hold input
|
ibusy := '1'; -- default is to hold input
|
ival := '0';
|
ival := '0';
|
ido := (others=>'0');
|
ido := (others=>'0');
|
|
|
Line 365... |
Line 401... |
n.attn(i) := '1'; -- set attention bit
|
n.attn(i) := '1'; -- set attention bit
|
end if;
|
end if;
|
end loop;
|
end loop;
|
|
|
has_attn := '0';
|
has_attn := '0';
|
|
snd_attn := '0';
|
|
|
if unsigned(r.attn) /= 0 then -- is any of the attn bits set ?
|
if unsigned(r.attn) /= 0 then -- is any of the attn bits set ?
|
has_attn := '1';
|
has_attn := '1';
|
|
if r.anena='1' and r.andone='0' then -- is attn notification to be send ?
|
|
snd_attn := '1';
|
|
n.monlamp := '1'; -- set lamp flag in rl_moni
|
|
end if;
|
end if;
|
end if;
|
|
|
ato_go := '0'; -- default: keep access timeout in reset
|
ato_go := '0'; -- default: keep access timeout in reset
|
ato_end := '0';
|
ato_end := '0';
|
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
|
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
|
Line 384... |
Line 426... |
end if;
|
end if;
|
|
|
case r.state is
|
case r.state is
|
when s_idle => -- s_idle: wait for sop --------------
|
when s_idle => -- s_idle: wait for sop --------------
|
ito_go := '1'; -- idle timeout active
|
ito_go := '1'; -- idle timeout active
|
if (r.anena='1' and -- if attn notification to send
|
if snd_attn = '1' then -- if attn notification to be send
|
has_attn='1' and r.andone='0') then
|
n.state := s_txito; -- next: send ito byte
|
n.state := s_txito; -- next send ito byte
|
|
else
|
else
|
ibusy := '0'; -- accept input
|
ibusy := '0'; -- accept input
|
if CP_ENA = '1' then -- if input
|
if RL_ENA = '1' then -- if input
|
if is_comma = '1' then -- if comma
|
if is_comma = '1' then -- if comma
|
case comma_typ is
|
case comma_typ is
|
when c_sop => -- if sop
|
when c_sop => -- if sop
|
crcreset := '1'; -- reset crc generators
|
crcreset := '1'; -- reset crc generators
|
n.state := s_txsop; -- next: echo it
|
n.state := s_txsop; -- next: echo it
|
Line 413... |
Line 454... |
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_txito => -- s_txito: send timeout symbol ------
|
when s_txito => -- s_txito: send timeout symbol ------
|
if has_attn = '1' then
|
if has_attn = '1' then
|
ido := c_rri_dat_attn; -- if attn pending: send attn symbol
|
ido := c_rlink_dat_attn; -- if attn pending: send attn symbol
|
n.andone := '1';
|
n.andone := '1';
|
else
|
else
|
ido := c_rri_dat_idle; -- otherwise: send idle symbol
|
ido := c_rlink_dat_idle; -- otherwise: send idle symbol
|
end if;
|
end if;
|
ival := '1';
|
ival := '1';
|
if CP_HOLD = '0' then -- wait for accept
|
if RL_HOLD = '0' then -- wait for accept
|
|
n.monattn := has_attn; -- signal on rl_moni
|
n.state := s_idle; -- next: wait for sop
|
n.state := s_idle; -- next: wait for sop
|
end if;
|
end if;
|
|
|
when s_txsop => -- s_txsop: send sop -----------------
|
when s_txsop => -- s_txsop: send sop -----------------
|
ido := c_rri_dat_sop; -- send sop character
|
ido := c_rlink_dat_sop; -- send sop character
|
ival := '1';
|
ival := '1';
|
if CP_HOLD = '0' then -- wait for accept
|
if RL_HOLD = '0' then -- wait for accept
|
n.state := s_rxcmd; -- next: read first command
|
n.state := s_rxcmd; -- next: read first command
|
end if;
|
end if;
|
|
|
when s_txnak => -- s_txnak: send nak -----------------
|
when s_txnak => -- s_txnak: send nak -----------------
|
ido := c_rri_dat_nak; -- send nak character
|
ido := c_rlink_dat_nak; -- send nak character
|
ival := '1';
|
ival := '1';
|
if CP_HOLD = '0' then -- wait for accept
|
if RL_HOLD = '0' then -- wait for accept
|
n.nakeop := '0';
|
n.nakeop := '0'; -- clear all 'do on nak' state flags
|
|
n.nakcerr := '0';
|
|
n.nakderr := '0';
|
|
if r.nakcerr = '1' then -- if setting cerr requested
|
|
n.cerr := '1'; -- do it
|
|
end if;
|
|
if r.nakderr = '1' then -- if settung derr requested
|
|
n.derr := '1'; -- do it
|
|
end if;
|
if r.nakeop = '1' then -- if eop after nak requested
|
if r.nakeop = '1' then -- if eop after nak requested
|
n.state := s_txeop; -- next: send eop
|
n.state := s_txeop; -- next: send eop
|
else
|
else
|
n.state := s_error; -- next: error state, wait for eop
|
n.state := s_error; -- next: error state, wait for eop
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_txeop => -- s_txeop: send eop -----------------
|
when s_txeop => -- s_txeop: send eop -----------------
|
ido := c_rri_dat_eop; -- send eop character
|
ido := c_rlink_dat_eop; -- send eop character
|
ival := '1';
|
ival := '1';
|
if CP_HOLD = '0' then -- wait for accept
|
if RL_HOLD = '0' then -- wait for accept
|
n.flush := '1'; -- send flush pulse
|
n.moneop := '1'; -- signal on rl_moni
|
n.state := s_idle; -- next: idle state, wait for sop
|
n.state := s_idle; -- next: idle state, wait for sop
|
end if;
|
end if;
|
|
|
when s_error => -- s_error: wait for eop -------------
|
when s_error => -- s_error: wait for eop -------------
|
ibusy := '0'; -- accept input
|
ibusy := '0'; -- accept input
|
if CP_ENA = '1' then
|
if RL_ENA = '1' then
|
if is_comma = '1' then -- if comma
|
if is_comma = '1' then -- if comma
|
case comma_typ is
|
case comma_typ is
|
when c_sop => -- if sop (unexpected)
|
when c_sop => -- if sop (unexpected)
|
n.state := s_txnak; -- next: send nak
|
n.state := s_txnak; -- next: send nak
|
when c_eop => -- if eop
|
when c_eop => -- if eop
|
Line 470... |
Line 520... |
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_rxcmd => -- s_rxcmd: wait for cmd -------------
|
when s_rxcmd => -- s_rxcmd: wait for cmd -------------
|
ibusy := '0'; -- accept input
|
ibusy := '0'; -- accept input
|
if CP_ENA = '1' then
|
if RL_ENA = '1' then
|
if is_comma = '1' then -- if comma
|
if is_comma = '1' then -- if comma
|
case comma_typ is
|
case comma_typ is
|
when c_sop => -- if sop (unexpected)
|
when c_sop => -- if sop (unexpected)
|
n.state := s_txnak; -- next: send nak
|
n.state := s_txnak; -- next: send nak
|
when c_eop => -- if eop
|
when c_eop => -- if eop
|
n.state := s_txeop; -- next: echo eop
|
n.state := s_txeop; -- next: echo eop
|
when c_nak => -- if nak
|
when c_nak => -- if nak
|
n.state := s_txnak; -- next: echo nak
|
n.state := s_txnak; -- next: echo nak
|
when others => null; --other commas: silently ignore
|
when others => null; --other commas: silently ignore
|
end case;
|
end case;
|
else
|
else -- if not comma
|
icrcena := '1'; -- update input crc
|
icrcena := '1'; -- update input crc
|
n.rcmd := idi8; -- latch read command code
|
n.rcmd := idi8; -- latch received command code
|
case CP_DI(c_rri_cmd_rbf_code) is
|
-- unless the command is stat
|
when c_rri_cmd_rreg | c_rri_cmd_rblk |
|
if RL_DI(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then
|
c_rri_cmd_wreg | c_rri_cmd_wblk |
|
n.nakcerr := '1'; -- set cerr on eop/nak abort
|
c_rri_cmd_init => -- for commands needing addr(data)
|
end if;
|
|
case RL_DI(c_rlink_cmd_rbf_code) is
|
|
when c_rlink_cmd_rreg |
|
|
c_rlink_cmd_rblk |
|
|
c_rlink_cmd_wreg |
|
|
c_rlink_cmd_wblk |
|
|
c_rlink_cmd_init => -- for commands needing addr(data)
|
n.state := s_rxaddr; -- next: read address
|
n.state := s_rxaddr; -- next: read address
|
when c_rri_cmd_stat | c_rri_cmd_attn => -- stat and attn commands
|
when c_rlink_cmd_stat |
|
|
c_rlink_cmd_attn => -- stat and attn commands
|
n.state := s_rxccrc; -- next: read command crc
|
n.state := s_rxccrc; -- next: read command crc
|
when others =>
|
when others =>
|
n.state := s_idle; -- if bad command abort here
|
n.state := s_txnak; -- next: send nak
|
end case; -- rcmd,ccmd always hold good cmd
|
end case; -- rcmd,ccmd always hold good cmd
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_rxaddr => -- s_rxaddr: wait for addr -----------
|
when s_rxaddr => -- s_rxaddr: wait for addr -----------
|
ibusy := '0'; -- accept input
|
ibusy := '0'; -- accept input
|
if CP_ENA = '1' then
|
if RL_ENA = '1' then
|
if is_comma = '1' then -- if comma
|
if is_comma = '1' then -- if comma
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
else
|
else
|
icrcena := '1'; -- update input crc
|
icrcena := '1'; -- update input crc
|
n.addr := idi8; -- latch read address
|
n.addr := idi8; -- latch read address
|
case r.rcmd(c_rri_cmd_rbf_code) is
|
case r.rcmd(c_rlink_cmd_rbf_code) is
|
when c_rri_cmd_rreg => -- for rreg command
|
when c_rlink_cmd_rreg => -- for rreg command
|
n.state := s_rxccrc; -- next: read command crc
|
n.state := s_rxccrc; -- next: read command crc
|
when c_rri_cmd_wreg | c_rri_cmd_init => -- for wreg, init command
|
when c_rlink_cmd_wreg |
|
|
c_rlink_cmd_init => -- for wreg, init command
|
n.state := s_rxdatl; -- next: read data lsb
|
n.state := s_rxdatl; -- next: read data lsb
|
when others => -- for rblk or wblk
|
when others => -- for rblk or wblk
|
n.state := s_rxcnt; -- next: read count
|
n.state := s_rxcnt; -- next: read count
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_rxdatl => -- s_rxdatl: wait for data low -------
|
when s_rxdatl => -- s_rxdatl: wait for data low -------
|
ibusy := '0'; -- accept input
|
ibusy := '0'; -- accept input
|
if CP_ENA = '1' then
|
if RL_ENA = '1' then
|
if is_comma = '1' then -- if comma
|
if is_comma = '1' then -- if comma
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
else
|
else
|
icrcena := '1'; -- update input crc
|
icrcena := '1'; -- update input crc
|
n.dil := idi8; -- latch data lsb part
|
n.dil := idi8; -- latch data lsb part
|
Line 530... |
Line 588... |
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_rxdath => -- s_rxdath: wait for data high ------
|
when s_rxdath => -- s_rxdath: wait for data high ------
|
ibusy := '0'; -- accept input
|
ibusy := '0'; -- accept input
|
if CP_ENA = '1' then
|
if RL_ENA = '1' then
|
if is_comma = '1' then -- if comma
|
if is_comma = '1' then -- if comma
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
else
|
else
|
icrcena := '1'; -- update input crc
|
icrcena := '1'; -- update input crc
|
n.dih := idi8; -- latch data msb part
|
n.dih := idi8; -- latch data msb part
|
if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_wblk then -- if wblk
|
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk
|
n.rbreq := '1';
|
n.rbaval := '1'; -- prepare rbus cycle
|
n.rbwe := '1';
|
n.state := s_wstart; -- next: start write reg
|
n.state := s_wreg; -- next: write reg
|
|
else -- otherwise
|
else -- otherwise
|
n.state := s_rxccrc; -- next: read command crc
|
n.state := s_rxccrc; -- next: read command crc
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_rxcnt => -- s_rxcnt: wait for count -----------
|
when s_rxcnt => -- s_rxcnt: wait for count -----------
|
ibusy := '0'; -- accept input
|
ibusy := '0'; -- accept input
|
if CP_ENA = '1' then
|
if RL_ENA = '1' then
|
if is_comma = '1' then -- if comma
|
if is_comma = '1' then -- if comma
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
else
|
else
|
icrcena := '1'; -- update input crc
|
icrcena := '1'; -- update input crc
|
n.cnt := idi8; -- latch count
|
n.cnt := idi8; -- latch count
|
Line 560... |
Line 617... |
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_rxccrc => -- s_rxccrc: wait for command crc ----
|
when s_rxccrc => -- s_rxccrc: wait for command crc ----
|
ibusy := '0'; -- accept input
|
ibusy := '0'; -- accept input
|
if CP_ENA = '1' then
|
if RL_ENA = '1' then
|
if is_comma = '1' then -- if comma
|
if is_comma = '1' then -- if comma
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
else
|
else
|
if idi8 /= ICRC_OUT then -- if crc error
|
if idi8 /= ICRC_OUT then -- if crc error
|
n.ccrc := '1'; -- set command crc error flag
|
-- unless the command is stat
|
|
if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then
|
|
n.cerr := '1'; -- set command error flag
|
|
end if;
|
n.state := s_txnak; -- next: send nak
|
n.state := s_txnak; -- next: send nak
|
else -- if crc ok
|
else -- if crc ok
|
n.state := s_txcmd; -- next: echo command
|
n.state := s_txcmd; -- next: echo command
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_txcmd => -- s_txcmd: send cmd -----------------
|
when s_txcmd => -- s_txcmd: send cmd -----------------
|
ido := '0' & r.rcmd; -- send read command
|
ido := '0' & r.rcmd; -- send read command
|
ival := '1';
|
ival := '1';
|
if CP_HOLD = '0' then -- wait for accept
|
if RL_HOLD = '0' then -- wait for accept
|
ocrcena := '1'; -- update output crc
|
ocrcena := '1'; -- update output crc
|
if r.rcmd(c_rri_cmd_rbf_code) /= c_rri_cmd_stat then -- unless stat
|
if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then --unless stat
|
n.ccmd := r.rcmd; -- latch read command in ccmd
|
n.ccmd := r.rcmd; -- latch current command in ccmd
|
n.stat := RB_STAT; -- latch external status bits
|
n.stat := RB_STAT; -- latch external status bits
|
n.ccrc := '0';
|
n.cerr := '0';
|
n.dcrc := '0';
|
n.derr := '0';
|
n.ioto := '0';
|
n.rbnak := '0';
|
n.ioerr := '0';
|
n.rberr := '0';
|
end if;
|
end if;
|
case r.rcmd(c_rri_cmd_rbf_code) is -- main command dispatcher
|
n.nakcerr := '0'; -- all command rx done up to here
|
when c_rri_cmd_rreg => -- rreg ----------------
|
|
n.rbreq := '1';
|
case r.rcmd(c_rlink_cmd_rbf_code) is -- main command dispatcher
|
n.state := s_rreg;
|
when c_rlink_cmd_rreg => -- rreg ----------------
|
when c_rri_cmd_rblk => -- rblk ----------------
|
n.rbaval := '1'; -- prepare rbus cycle
|
|
n.state := s_rstart; -- next: start read reg
|
|
when c_rlink_cmd_rblk => -- rblk ----------------
|
n.state := s_txcnt;
|
n.state := s_txcnt;
|
when c_rri_cmd_wreg => -- wreg ----------------
|
when c_rlink_cmd_wreg => -- wreg ----------------
|
n.rbreq := '1';
|
n.rbaval := '1'; -- prepare rbus cycle
|
n.rbwe := '1';
|
n.state := s_wstart; -- next: start write reg
|
n.state := s_wreg;
|
when c_rlink_cmd_wblk => -- wblk ----------------
|
when c_rri_cmd_wblk => -- wblk ----------------
|
n.nakderr := '1'; -- set derr on eop/nak abort
|
n.state := s_rxdatl;
|
n.state := s_rxdatl;
|
when c_rri_cmd_stat => -- stat ----------------
|
when c_rlink_cmd_stat => -- stat ----------------
|
n.state := s_txccmd;
|
n.state := s_txccmd;
|
when c_rri_cmd_attn => -- attn ----------------
|
when c_rlink_cmd_attn => -- attn ----------------
|
n.state := s_attn;
|
n.state := s_attn;
|
|
|
when c_rri_cmd_init => -- init ----------------
|
when c_rlink_cmd_init => -- init ----------------
|
n.rbinit := '1'; -- send init pulse
|
n.rbinit := '1'; -- send init pulse
|
if r.addr(7 downto 3) = "11111" then -- is internal init
|
if r.addr(7 downto 3) = "11111" then -- is internal init
|
if r.addr(2 downto 0) = "111" then -- is rri init
|
if r.addr(2 downto 0) = "111" then -- is rri init
|
n.anena := r.dih(c_rri_iint_rbf_anena - 8);
|
n.anena := r.dih(c_rlink_iint_rbf_anena - 8);
|
n.itoena := r.dih(c_rri_iint_rbf_itoena - 8);
|
n.itoena := r.dih(c_rlink_iint_rbf_itoena - 8);
|
n.itoval := r.dil(ITOWIDTH-1 downto 0);
|
n.itoval := r.dil(ITOWIDTH-1 downto 0);
|
-- note: itocnt will load in next
|
-- note: itocnt will load in next
|
-- cycle because ito_go=0, so no
|
-- cycle because ito_go=0, so no
|
-- action required here
|
-- action required here
|
|
|
Line 628... |
Line 690... |
end if;
|
end if;
|
|
|
when s_txcnt => -- s_txcnt: send cnt -----------------
|
when s_txcnt => -- s_txcnt: send cnt -----------------
|
ido := '0' & r.cnt; -- send cnt
|
ido := '0' & r.cnt; -- send cnt
|
ival := '1';
|
ival := '1';
|
if CP_HOLD = '0' then -- wait for accept
|
if RL_HOLD = '0' then -- wait for accept
|
ocrcena := '1'; -- update output crc
|
ocrcena := '1'; -- update output crc
|
n.rbreq := '1';
|
n.rbaval := '1'; -- prepare rbus cycle
|
n.state := s_rreg; -- next: first read reg
|
n.state := s_rstart; -- next: start first read reg
|
end if;
|
end if;
|
|
|
when s_rreg => -- s_rreg: reg or blk read -----------
|
when s_rstart => -- s_rstart: start reg or blk read ---
|
-- this state handles all rbus reads. Expects that previous state
|
n.rbaval := '1'; -- start actual read cycle
|
-- sets n.rbreq := '1' to start an rbus read cycle
|
n.rbre := '1';
|
|
n.state := s_rreg; -- next: reg read
|
|
|
|
when s_rreg => -- s_rreg: do reg or blk read --------
|
|
-- this state handles all rbus reads
|
ato_go := '1'; -- activate timeout counter
|
ato_go := '1'; -- activate timeout counter
|
if RB_SRES.err = '1' then -- latch error flag
|
if RB_SRES.err = '1' then -- latch rbus error flag
|
n.ioerr := '1';
|
n.rberr := '1';
|
end if;
|
end if;
|
n.doh := RB_SRES.dout(15 downto 8); -- latch data
|
n.doh := RB_SRES.dout(15 downto 8); -- latch data
|
n.dol := RB_SRES.dout( 7 downto 0);
|
n.dol := RB_SRES.dout( 7 downto 0);
|
n.stat := RB_STAT; -- latch external status bits
|
n.stat := RB_STAT; -- latch external status bits
|
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
|
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
|
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
|
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
|
n.ioto := '1'; -- set timeout flag
|
n.rbnak := '1'; -- set rbus nak flag
|
elsif RB_SRES.ack = '0' then -- if non-busy and no ack
|
elsif RB_SRES.ack = '0' then -- if non-busy and no ack
|
n.ioto := '1'; -- set timeout flag
|
n.rbnak := '1'; -- set rbus nak flag
|
end if;
|
end if;
|
n.state := s_txdatl; -- next: send data lsb
|
n.state := s_txdatl; -- next: send data lsb
|
else -- otherwise rbus read continues
|
else -- otherwise rbus read continues
|
n.rbreq := '1'; -- extend req
|
n.rbaval := '1'; -- extend cycle
|
|
n.rbre := '1';
|
end if;
|
end if;
|
|
|
when s_txdatl => -- s_txdatl: send data low -----------
|
when s_txdatl => -- s_txdatl: send data low -----------
|
ido := '0' & r.dol; -- send data
|
ido := '0' & r.dol; -- send data
|
ival := '1';
|
ival := '1';
|
if CP_HOLD = '0' then -- wait for accept
|
if RL_HOLD = '0' then -- wait for accept
|
ocrcena := '1'; -- update output crc
|
ocrcena := '1'; -- update output crc
|
n.state := s_txdath; -- next: send data msb
|
n.state := s_txdath; -- next: send data msb
|
end if;
|
end if;
|
|
|
when s_txdath => -- s_txdath: send data high
|
when s_txdath => -- s_txdath: send data high
|
ido := '0' & r.doh; -- send data
|
ido := '0' & r.doh; -- send data
|
ival := '1';
|
ival := '1';
|
if CP_HOLD = '0' then -- wait for accept
|
if RL_HOLD = '0' then -- wait for accept
|
ocrcena := '1'; -- update output crc
|
ocrcena := '1'; -- update output crc
|
if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk
|
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
|
n.state := s_blk; -- next: block count handling
|
n.state := s_blk; -- next: block count handling
|
else -- otherwise
|
else -- otherwise
|
n.state := s_txstat; -- next: send stat
|
n.state := s_txstat; -- next: send stat
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_wreg => -- s_wreg: reg or blk write ----------
|
when s_wstart => -- s_wstart: start reg or blk write --
|
-- this state handles all rbus writes. Expects that previous state
|
n.rbaval := '1'; -- start actual write cycle
|
-- sets n.rbreq := '1' and n.rbwe := '1' to start an rbus write cycle
|
n.rbwe := '1';
|
|
n.state := s_wreg; -- next: reg write
|
|
|
|
when s_wreg => -- s_wreg: do reg or blk write -------
|
|
-- this state handles all rbus writes
|
ato_go := '1'; -- activate timeout counter
|
ato_go := '1'; -- activate timeout counter
|
if RB_SRES.err = '1' then -- latch error flag
|
if RB_SRES.err = '1' then -- latch rbus error flag
|
n.ioerr := '1';
|
n.rberr := '1';
|
end if;
|
end if;
|
n.stat := RB_STAT; -- latch external status bits
|
n.stat := RB_STAT; -- latch external status bits
|
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
|
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
|
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
|
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
|
n.ioto := '1'; -- set timeout flag
|
n.rbnak := '1'; -- set rbus nak flag
|
elsif RB_SRES.ack='0' then -- if non-busy and no ack
|
elsif RB_SRES.ack='0' then -- if non-busy and no ack
|
n.ioto := '1'; -- set timeout flag
|
n.rbnak := '1'; -- set rbus nak flag
|
end if;
|
end if;
|
if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_wblk then -- if wblk
|
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk
|
n.state := s_blk; -- next: block count handling
|
n.state := s_blk; -- next: block count handling
|
else -- otherwise
|
else -- otherwise
|
n.state := s_txstat; -- next: send stat
|
n.state := s_txstat; -- next: send stat
|
end if;
|
end if;
|
else -- otherwise rbus write continues
|
else -- otherwise rbus write continues
|
n.rbreq := '1'; -- extend req
|
n.rbaval := '1'; -- extend cycle
|
n.rbwe := '1'; -- extend we
|
n.rbwe := '1';
|
end if;
|
end if;
|
|
|
when s_blk => -- s_blk: block count handling -------
|
when s_blk => -- s_blk: block count handling -------
|
n.cnt := unsigned(r.cnt) - 1; -- decrement transfer count
|
n.cnt := unsigned(r.cnt) - 1; -- decrement transfer count
|
if unsigned(r.cnt) = 0 then -- if last transfer
|
if unsigned(r.cnt) = 0 then -- if last transfer
|
if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk
|
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
|
n.state := s_txstat; -- next: send stat
|
n.state := s_txstat; -- next: send stat
|
else -- otherwise
|
else -- otherwise
|
n.state := s_rxdcrc; -- next: read data crc
|
n.state := s_rxdcrc; -- next: read data crc
|
end if;
|
end if;
|
|
|
else -- otherwise more to transfer
|
else -- otherwise more to transfer
|
if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk
|
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
|
n.rbreq := '1';
|
n.rbaval := '1'; -- prepare rbus cycle
|
n.state := s_rreg; -- next: read blk
|
n.state := s_rstart; -- next: start read blk
|
else -- otherwise
|
else -- otherwise
|
n.state := s_rxdatl; -- next: read data
|
n.state := s_rxdatl; -- next: read data
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_rxdcrc => -- s_rxdcrc: wait for data crc -------
|
when s_rxdcrc => -- s_rxdcrc: wait for data crc -------
|
ibusy := '0'; -- accept input
|
ibusy := '0'; -- accept input
|
if CP_ENA = '1' then
|
if RL_ENA = '1' then
|
if is_comma = '1' then -- if comma
|
if is_comma = '1' then -- if comma
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
do_comma_abort(n.state, n.nakeop, comma_typ);
|
else
|
else
|
if idi8 /= ICRC_OUT then -- if crc error
|
if idi8 /= ICRC_OUT then -- if crc error
|
n.dcrc := '1'; -- set data crc error flag
|
n.derr := '1'; -- set data error flag
|
end if;
|
end if;
|
n.state := s_txstat; -- next: echo command
|
n.state := s_txstat; -- next: echo command
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
Line 740... |
Line 811... |
n.state := s_txdatl; -- next: send data lsb
|
n.state := s_txdatl; -- next: send data lsb
|
|
|
when s_txccmd => -- s_txccmd: send last command
|
when s_txccmd => -- s_txccmd: send last command
|
ido := '0' & r.ccmd; -- send last accepted command
|
ido := '0' & r.ccmd; -- send last accepted command
|
ival := '1';
|
ival := '1';
|
if CP_HOLD = '0' then -- wait for accept
|
if RL_HOLD = '0' then -- wait for accept
|
ocrcena := '1'; -- update output crc
|
ocrcena := '1'; -- update output crc
|
n.state := s_txdatl; -- next: send last data lsb
|
n.state := s_txdatl; -- next: send last data lsb
|
end if;
|
end if;
|
|
|
when s_txstat => -- s_txstat: send status -------------
|
when s_txstat => -- s_txstat: send status -------------
|
ido := (others=>'0');
|
ido := (others=>'0');
|
ido(c_rri_stat_rbf_stat) := r.stat;
|
ido(c_rlink_stat_rbf_stat) := r.stat;
|
ido(c_rri_stat_rbf_attn) := has_attn;
|
ido(c_rlink_stat_rbf_attn) := has_attn;
|
ido(c_rri_stat_rbf_ccrc) := r.ccrc;
|
ido(c_rlink_stat_rbf_cerr) := r.cerr;
|
ido(c_rri_stat_rbf_dcrc) := r.dcrc;
|
ido(c_rlink_stat_rbf_derr) := r.derr;
|
ido(c_rri_stat_rbf_ioto) := r.ioto;
|
ido(c_rlink_stat_rbf_rbnak) := r.rbnak;
|
ido(c_rri_stat_rbf_ioerr) := r.ioerr;
|
ido(c_rlink_stat_rbf_rberr) := r.rberr;
|
ival := '1';
|
ival := '1';
|
if CP_HOLD ='0' then -- wait for accept
|
if RL_HOLD ='0' then -- wait for accept
|
ocrcena := '1'; -- update output crc
|
ocrcena := '1'; -- update output crc
|
n.state := s_txcrc; -- next: send crc
|
n.state := s_txcrc; -- next: send crc
|
end if;
|
end if;
|
|
|
when s_txcrc => -- s_txcrc: send crc -----------------
|
when s_txcrc => -- s_txcrc: send crc -----------------
|
ido := "0" & OCRC_OUT; -- send crc code
|
ido := "0" & OCRC_OUT; -- send crc code
|
ival := '1';
|
ival := '1';
|
if CP_HOLD = '0' then -- wait for accept
|
if RL_HOLD = '0' then -- wait for accept
|
|
-- if dcrc seen in wblk
|
|
if r.rcmd(c_rlink_cmd_rbf_code)=c_rlink_cmd_wblk and r.derr='1' then
|
|
n.state := s_txnak; -- next: send nak
|
|
else -- otherwise
|
|
n.nakcerr := '0'; -- clear 'set on nak' requests
|
|
n.nakderr := '0';
|
n.state := s_rxcmd; -- next: read command or eop
|
n.state := s_rxcmd; -- next: read command or eop
|
end if;
|
end if;
|
|
end if;
|
|
|
when others => null; -- <> --------------------------------
|
when others => null; -- <> --------------------------------
|
end case;
|
end case;
|
|
|
if ato_go = '0' then -- handle access timeout counter
|
if ato_go = '0' then -- handle access timeout counter
|
Line 785... |
Line 863... |
end if;
|
end if;
|
end if;
|
end if;
|
|
|
N_REGS <= n;
|
N_REGS <= n;
|
|
|
CP_BUSY <= ibusy;
|
RL_BUSY <= ibusy;
|
CP_DO <= ido;
|
RL_DO <= ido;
|
CP_VAL <= ival;
|
RL_VAL <= ival;
|
CP_FLUSH <= r.flush;
|
|
|
RL_MONI.eop <= r.moneop;
|
|
RL_MONI.attn <= r.monattn;
|
|
RL_MONI.lamp <= r.monlamp;
|
|
|
RB_MREQ <= rb_mreq_init;
|
RB_MREQ <= rb_mreq_init;
|
RB_MREQ.req <= r.rbreq;
|
RB_MREQ.aval <= r.rbaval;
|
|
RB_MREQ.re <= r.rbre;
|
RB_MREQ.we <= r.rbwe;
|
RB_MREQ.we <= r.rbwe;
|
RB_MREQ.init <= r.rbinit;
|
RB_MREQ.init <= r.rbinit;
|
RB_MREQ.addr <= r.addr;
|
RB_MREQ.addr <= r.addr;
|
RB_MREQ.din <= r.dih & r.dil;
|
RB_MREQ.din <= r.dih & r.dil;
|
|
|