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-- $Id: rlink_mon.vhd 427 2011-11-19 21:04:11Z mueller $
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-- $Id: rlink_mon.vhd 444 2011-12-25 10:04:58Z mueller $
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--
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Test bench: -
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-- Test bench: -
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-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-12-23 444 3.1 CLK_CYCLE now integer
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-- 2011-11-19 427 3.0.2 now numeric_std clean
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-- 2011-11-19 427 3.0.2 now numeric_std clean
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-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
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-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
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-- 2010-12-22 346 3.0 renamed rritb_cpmon -> rlink_mon
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-- 2010-12-22 346 3.0 renamed rritb_cpmon -> rlink_mon
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-- 2010-06-11 303 2.5.1 fix data9 assignment, always proper width now
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-- 2010-06-11 303 2.5.1 fix data9 assignment, always proper width now
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-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
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-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
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entity rlink_mon is -- rlink monitor
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entity rlink_mon is -- rlink monitor
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generic (
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generic (
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DWIDTH : positive := 9); -- data port width (8 or 9)
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DWIDTH : positive := 9); -- data port width (8 or 9)
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
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CLK_CYCLE : in integer := 0; -- clock cycle number
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ENA : in slbit := '1'; -- enable monitor output
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ENA : in slbit := '1'; -- enable monitor output
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RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
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RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
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RL_ENA : in slbit; -- rlink: data enable
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RL_ENA : in slbit; -- rlink: data enable
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RL_BUSY : in slbit; -- rlink: data busy
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RL_BUSY : in slbit; -- rlink: data busy
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RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
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RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
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