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-- $Id: rlink_mon_sb.vhd 427 2011-11-19 21:04:11Z mueller $
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-- $Id: rlink_mon_sb.vhd 444 2011-12-25 10:04:58Z mueller $
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--
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: rlink_mon_sb - sim
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-- Module Name: rlink_mon_sb - sim
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-- Description: simbus wrapper for rlink monitor
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-- Description: simbus wrapper for rlink monitor
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--
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--
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-- Dependencies: simbus
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-- Dependencies: simbus
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-- simlib/simclkcnt
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-- rlink_mon
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-- Test bench: -
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-- Test bench: -
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-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-12-23 444 3.1 use simclkcnt instead of simbus global
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-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
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-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
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-- 2010-12-22 346 3.0 renamed rritb_cpmon_sb -> rlink_mon_sb
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-- 2010-12-22 346 3.0 renamed rritb_cpmon_sb -> rlink_mon_sb
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-- 2010-05-02 287 1.0.1 use sbcntl_sbf_cpmon def
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-- 2010-05-02 287 1.0.1 use sbcntl_sbf_cpmon def
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-- 2007-08-25 75 1.0 Initial version
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-- 2007-08-25 75 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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architecture sim of rlink_mon_sb is
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architecture sim of rlink_mon_sb is
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signal ENA : slbit := '0';
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signal ENA : slbit := '0';
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signal CLK_CYCLE : integer := 0;
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begin
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begin
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assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
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assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
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report "assert(ENAPIN in SB_CNTL'range)" severity failure;
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report "assert(ENAPIN in SB_CNTL'range)" severity failure;
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CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
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ENA <= to_x01(SB_CNTL(ENAPIN));
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ENA <= to_x01(SB_CNTL(ENAPIN));
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CPMON : rlink_mon
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CPMON : rlink_mon
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generic map (
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generic map (
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DWIDTH => DWIDTH)
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DWIDTH => DWIDTH)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CLK_CYCLE => SB_CLKCYCLE,
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CLK_CYCLE => CLK_CYCLE,
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ENA => ENA,
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ENA => ENA,
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RL_DI => RL_DI,
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RL_DI => RL_DI,
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RL_ENA => RL_ENA,
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RL_ENA => RL_ENA,
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RL_BUSY => RL_BUSY,
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RL_BUSY => RL_BUSY,
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RL_DO => RL_DO,
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RL_DO => RL_DO,
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