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-- $Id: rlinklib.vhd 427 2011-11-19 21:04:11Z mueller $
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-- $Id: rlinklib.vhd 442 2011-12-23 10:03:28Z mueller $
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--
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Dependencies: -
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-- Dependencies: -
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-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-12-21 442 3.2.1 retire old, deprecated interfaces
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-- 2011-12-09 437 3.2 add rlink_core8
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-- 2011-11-18 427 3.1.3 now numeric_std clean
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-- 2011-11-18 427 3.1.3 now numeric_std clean
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-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
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-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
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-- new rlink_serport interface;
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-- new rlink_serport interface;
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-- rename rlink_core_serport->rlink_base_serport
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-- rename rlink_core_serport->rlink_base_serport
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-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
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-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.rblib.all;
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use work.rblib.all;
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use work.serport.all;
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package rlinklib is
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package rlinklib is
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constant c_rlink_cpref : slv4 := "1000"; -- default comma prefix
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constant c_rlink_cpref : slv4 := "1000"; -- default comma prefix
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constant c_rlink_ncomm : positive := 4; -- number commas (sop,eop,nak,attn)
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constant c_rlink_ncomm : positive := 4; -- number commas (sop,eop,nak,attn)
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-- ise 13.1 xst can bug check if generic defaults in a package are defined via
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-- ise 13.1 xst can bug check if generic defaults in a package are defined via
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-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok.
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-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok.
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-- As workaround the ibus default addresses are defined here as constant.
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-- As workaround the ibus default addresses are defined here as constant.
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constant rbaddr_rlink_serport : slv8 := slv(to_unsigned(2#11111110#,8));
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constant rbaddr_rlink_serport : slv8 := slv(to_unsigned(2#11111110#,8));
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-- this definition logically belongs into the 'for test benches' section'
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-- must be here because it is needed as generic default in rlink_core8
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-- simbus sb_cntl field usage for rlink
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constant sbcntl_sbf_rlmon : integer := 15;
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component rlink_core is -- rlink core with 9bit iface
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component rlink_core is -- rlink core with 9bit iface
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generic (
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generic (
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ATOWIDTH : positive := 5; -- access timeout counter width
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ATOWIDTH : positive := 5; -- access timeout counter width
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ITOWIDTH : positive := 6); -- idle timeout counter width
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ITOWIDTH : positive := 6); -- idle timeout counter width
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port (
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port (
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RL_VAL : out slbit; -- rlink 9b: data valid
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RL_VAL : out slbit; -- rlink 9b: data valid
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RL_HOLD : in slbit := '0' -- rlink 9b: data hold
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RL_HOLD : in slbit := '0' -- rlink 9b: data hold
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);
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);
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end component;
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end component;
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component rlink_rlb2rl is -- rlink 8 bit(rlb) to 9 bit(rl) adapter
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component rlink_core8 is -- rlink core with 8bit iface
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generic (
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CPREF : slv4 := c_rlink_cpref; -- comma prefix
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IFAWIDTH : natural := 5; -- input fifo address width (0=none)
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OFAWIDTH : natural := 5); -- output fifo address width (0=none)
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RLB_DI : in slv8; -- rlink 8b: data in
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RLB_ENA : in slbit; -- rlink 8b: data enable
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RLB_BUSY : out slbit; -- rlink 8b: data busy
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RLB_DO : out slv8; -- rlink 8b: data out
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RLB_VAL : out slbit; -- rlink 8b: data valid
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RLB_HOLD : in slbit; -- rlink 8b: data hold
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IFIFO_SIZE : out slv4; -- input fifo size (4 msb's)
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OFIFO_SIZE : out slv4; -- output fifo fill (4 msb's)
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RL_DI : out slv9; -- rlink 9b: data in
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RL_ENA : out slbit; -- rlink 9b: data enable
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RL_BUSY : in slbit; -- rlink 9b: data busy
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RL_DO : in slv9; -- rlink 9b: data out
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RL_VAL : in slbit; -- rlink 9b: data valid
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RL_HOLD : out slbit -- rlink 9b: data hold
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);
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end component;
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-- this definition logically belongs into the 'for test benches' section'
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-- must be here because it is needed as generic default in rlink_base
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-- simbus sb_cntl field usage for rlink
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constant sbcntl_sbf_rlmon : integer := 15;
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component rlink_base is -- rlink base: core+rl2rlb+rlmon+rbmon
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-- with buffered 8bit interface
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generic (
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generic (
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ATOWIDTH : positive := 5; -- access timeout counter width
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ATOWIDTH : positive := 5; -- access timeout counter width
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ITOWIDTH : positive := 6; -- idle timeout counter width
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ITOWIDTH : positive := 6; -- idle timeout counter width
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CPREF : slv4 := c_rlink_cpref; -- comma prefix
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CPREF : slv4 := c_rlink_cpref; -- comma prefix
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IFAWIDTH : natural := 5; -- input fifo address width (0=none)
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OFAWIDTH : natural := 5; -- output fifo address width (0=none)
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ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
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ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
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ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none)
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ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none)
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
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CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
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RLB_ENA : in slbit; -- rlink 8b: data enable
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RLB_ENA : in slbit; -- rlink 8b: data enable
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RLB_BUSY : out slbit; -- rlink 8b: data busy
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RLB_BUSY : out slbit; -- rlink 8b: data busy
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RLB_DO : out slv8; -- rlink 8b: data out
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RLB_DO : out slv8; -- rlink 8b: data out
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RLB_VAL : out slbit; -- rlink 8b: data valid
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RLB_VAL : out slbit; -- rlink 8b: data valid
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RLB_HOLD : in slbit; -- rlink 8b: data hold
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RLB_HOLD : in slbit; -- rlink 8b: data hold
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IFIFO_SIZE : out slv4; -- input fifo size (4 msb's)
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OFIFO_SIZE : out slv4; -- output fifo fill (4 msb's)
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RL_MONI : out rl_moni_type; -- rlink: monitor port
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RL_MONI : out rl_moni_type; -- rlink: monitor port
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16; -- rbus: look at me
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RB_LAM : in slv16; -- rbus: look at me
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RB_STAT : in slv3 -- rbus: status flags
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RB_STAT : in slv3 -- rbus: status flags
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);
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);
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end component;
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end component;
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type rl_ser_moni_type is record -- rlink_serport monitor port
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--
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rxerr : slbit; -- rx err
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-- core + concrete_interface combo's
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rxdrop : slbit; -- rx drop
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--
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rxact : slbit; -- rx active
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txact : slbit; -- tx active
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abact : slbit; -- ab active
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abdone : slbit; -- ab done
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clkdiv : slv16; -- clock divider
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end record rl_ser_moni_type;
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constant rl_ser_moni_init : rl_ser_moni_type :=
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('0','0', -- rxerr,rxdrop
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'0','0', -- rxact,txact
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'0','0', -- abact,abdone
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(others=>'0')); -- clkdiv
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constant c_rlink_serport_rbf_fena: integer := 12; --
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subtype c_rlink_serport_rbf_fwidth is integer range 11 downto 9; --
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subtype c_rlink_serport_rbf_fdelay is integer range 8 downto 6; --
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subtype c_rlink_serport_rbf_rtsoff is integer range 5 downto 3; --
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subtype c_rlink_serport_rbf_rtson is integer range 2 downto 0; --
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component rlink_serport is -- rlink serport adapter
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generic (
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RB_ADDR : slv8 := rbaddr_rlink_serport;
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT : natural := 15); -- clk divider initial/reset setting
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- 1 usec clock enable
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CE_MSEC : in slbit; -- 1 msec clock enable
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RESET : in slbit; -- reset
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RXSD : in slbit; -- receive serial data (board view)
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TXSD : out slbit; -- transmit serial data (board view)
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CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
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RTS_N : out slbit; -- request to send (act.low, board view)
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RLB_DI : out slv8; -- rlink 8b: data in
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RLB_ENA : out slbit; -- rlink 8b: data enable
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RLB_BUSY : in slbit; -- rlink 8b: data busy
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RLB_DO : in slv8; -- rlink 8b: data out
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RLB_VAL : in slbit; -- rlink 8b: data valid
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RLB_HOLD : out slbit; -- rlink 8b: data hold
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RB_MREQ : in rb_mreq_type; -- rbus: request (for inits only)
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IFIFO_SIZE : in slv4; -- rlink_rlb2rb: input fifo size
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RL_MONI : in rl_moni_type; -- rlink_core: monitor port
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RL_SER_MONI : out rl_ser_moni_type -- rlink_serport: monitor port
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);
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end component;
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component rlink_base_serport is -- rlink base+serport combo
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component rlink_sp1c is -- rlink_core8+serport_1clock combo
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generic (
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generic (
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ATOWIDTH : positive := 5; -- access timeout counter width
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ATOWIDTH : positive := 5; -- access timeout counter width
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ITOWIDTH : positive := 6; -- idle timeout counter width
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ITOWIDTH : positive := 6; -- idle timeout counter width
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CPREF : slv4 := c_rlink_cpref; -- comma prefix
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CPREF : slv4 := c_rlink_cpref; -- comma prefix
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IFAWIDTH : natural := 5; -- input fifo address width (0=none)
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IFAWIDTH : natural := 5; -- input fifo address width (0=none)
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OFAWIDTH : natural := 5; -- output fifo address width (0=none)
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OFAWIDTH : natural := 5; -- output fifo address width (0=none)
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ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
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ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
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ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
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ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
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RB_ADDR : slv8 := rbaddr_rlink_serport;
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CDWIDTH : positive := 13; -- clk divider width
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT : natural := 15); -- clk divider initial/reset setting
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CDINIT : natural := 15); -- clk divider initial/reset setting
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- 1 usec clock enable
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CE_USEC : in slbit; -- 1 usec clock enable
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CE_MSEC : in slbit; -- 1 msec clock enable
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CE_MSEC : in slbit; -- 1 msec clock enable
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CE_INT : in slbit := '0'; -- rri ito time unit clock enable
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CE_INT : in slbit := '0'; -- rri ito time unit clock enable
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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ENAXON : in slbit; -- enable xon/xoff handling
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ENAESC : in slbit; -- enable xon/xoff escaping
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RXSD : in slbit; -- receive serial data (board view)
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RXSD : in slbit; -- receive serial data (board view)
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TXSD : out slbit; -- transmit serial data (board view)
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TXSD : out slbit; -- transmit serial data (board view)
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CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
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CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
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RTS_N : out slbit; -- request to send (act.low, board view)
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RTS_N : out slbit; -- request to send (act.low, board view)
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16; -- rbus: look at me
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RB_LAM : in slv16; -- rbus: look at me
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RB_STAT : in slv3; -- rbus: status flags
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RB_STAT : in slv3; -- rbus: status flags
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RL_MONI : out rl_moni_type; -- rlink_core: monitor port
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RL_MONI : out rl_moni_type; -- rlink_core: monitor port
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RL_SER_MONI : out rl_ser_moni_type -- rlink_serport: monitor port
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SER_MONI : out serport_moni_type -- serport: monitor port
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);
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);
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end component;
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end component;
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--
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--
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-- components for use in test benches (not synthesizable)
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-- components for use in test benches (not synthesizable)
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