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-- $Id: rrilib.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: rlinklib.vhd 348 2010-12-26 15:23:44Z mueller $
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--
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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| Line 10... |
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Package Name: rrilib
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-- Package Name: rlinklib
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-- Description: Remote Register Interface components
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-- Description: Definitions for rlink interface and bus entities
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
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-- new rlink_serport interface;
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-- rename rlink_core_serport->rlink_base_serport
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-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
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-- 2010-12-22 346 3.1 rename: [cd]crc->[cd]err, ioto->rbnak, ioerr->rberr
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-- 2010-12-04 343 3.0 move rbus components to rbus/rblib; renames
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|
-- rri_ -> rlink and c_rri -> c_rlink;
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-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
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-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
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-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
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-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
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-- 2010-06-03 300 2.1.5 use FAWIDTH=5 for rri_serport
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-- 2010-06-03 300 2.1.5 use FAWIDTH=5 for rri_serport
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-- 2010-05-02 287 2.1.4 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
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-- 2010-05-02 287 2.1.4 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
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-- drop RP_IINT from interfaces; drop RTSFLUSH generic
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-- drop RP_IINT from interfaces; drop RTSFLUSH generic
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| Line 37... |
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-- 2007-09-09 81 1.0 Initial version
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-- 2007-09-09 81 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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|
|
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
use ieee.std_logic_arith.all;
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|
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use work.slvtypes.all;
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use work.slvtypes.all;
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|
use work.rblib.all;
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|
|
|
package rlinklib is
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|
|
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constant c_rlink_cpref : slv4 := "1000"; -- default comma prefix
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constant c_rlink_ncomm : positive := 4; -- number commas (sop,eop,nak,attn)
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|
|
package rrilib is
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constant c_rlink_dat_idle : slv9 := "100000000";
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constant c_rlink_dat_sop : slv9 := "100000001";
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constant c_rlink_dat_eop : slv9 := "100000010";
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constant c_rlink_dat_nak : slv9 := "100000011";
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constant c_rlink_dat_attn : slv9 := "100000100";
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|
|
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constant c_rlink_cmd_rreg : slv3 := "000";
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constant c_rlink_cmd_rblk : slv3 := "001";
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constant c_rlink_cmd_wreg : slv3 := "010";
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constant c_rlink_cmd_wblk : slv3 := "011";
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constant c_rlink_cmd_stat : slv3 := "100";
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constant c_rlink_cmd_attn : slv3 := "101";
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constant c_rlink_cmd_init : slv3 := "110";
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|
|
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constant c_rlink_iint_rbf_anena: integer := 15; -- anena flag
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constant c_rlink_iint_rbf_itoena: integer := 14; -- itoena flag
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subtype c_rlink_iint_rbf_itoval is integer range 7 downto 0; -- command code
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subtype c_rlink_cmd_rbf_seq is integer range 7 downto 3; -- sequence number
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subtype c_rlink_cmd_rbf_code is integer range 2 downto 0; -- command code
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|
|
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subtype c_rlink_stat_rbf_stat is integer range 7 downto 5; -- ext status bits
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constant c_rlink_stat_rbf_attn: integer := 4; -- attention flags set
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constant c_rlink_stat_rbf_cerr: integer := 3; -- command error
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constant c_rlink_stat_rbf_derr: integer := 2; -- data error
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constant c_rlink_stat_rbf_rbnak: integer := 1; -- rbus no ack or timeout
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constant c_rlink_stat_rbf_rberr: integer := 0; -- rbus err bit set
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|
|
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type rl_moni_type is record -- rlink_core monitor port
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eop : slbit; -- eop send in last cycle
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attn : slbit; -- attn send in last cycle
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lamp : slbit; -- attn (lam) pending
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end record rl_moni_type;
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|
|
constant c_rri_dat_idle : slv9 := "100000000";
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constant rl_moni_init : rl_moni_type :=
|
constant c_rri_dat_sop : slv9 := "100000001";
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('0','0','0'); -- eop,attn,lamp
|
constant c_rri_dat_eop : slv9 := "100000010";
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|
constant c_rri_dat_nak : slv9 := "100000011";
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constant c_rri_dat_attn : slv9 := "100000100";
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|
|
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constant c_rri_cmd_rreg : slv3 := "000";
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|
constant c_rri_cmd_rblk : slv3 := "001";
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constant c_rri_cmd_wreg : slv3 := "010";
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constant c_rri_cmd_wblk : slv3 := "011";
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constant c_rri_cmd_stat : slv3 := "100";
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constant c_rri_cmd_attn : slv3 := "101";
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constant c_rri_cmd_init : slv3 := "110";
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|
|
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constant c_rri_iint_rbf_anena: integer := 15; -- anena flag
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constant c_rri_iint_rbf_itoena: integer := 14; -- itoena flag
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subtype c_rri_iint_rbf_itoval is integer range 7 downto 0; -- command code
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subtype c_rri_cmd_rbf_seq is integer range 7 downto 3; -- sequence number
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subtype c_rri_cmd_rbf_code is integer range 2 downto 0; -- command code
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|
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subtype c_rri_stat_rbf_stat is integer range 7 downto 5; -- ext status bits
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constant c_rri_stat_rbf_attn: integer := 4; -- attention flags set
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constant c_rri_stat_rbf_ccrc: integer := 3; -- command crc error
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constant c_rri_stat_rbf_dcrc: integer := 2; -- data crc error
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constant c_rri_stat_rbf_ioto: integer := 1; -- i/o time out
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constant c_rri_stat_rbf_ioerr: integer := 0; -- i/o error
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|
|
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type rb_mreq_type is record -- rribus - master request
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req : slbit; -- request
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we : slbit; -- write enable
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init : slbit; -- init
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addr : slv8; -- address
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din : slv16; -- data (input to slave)
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end record rb_mreq_type;
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|
|
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constant rb_mreq_init : rb_mreq_type :=
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|
('0','0','0', -- req, we, init
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(others=>'0'), -- addr
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(others=>'0')); -- din
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|
|
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type rb_sres_type is record -- rribus - slave response
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ack : slbit; -- acknowledge
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busy : slbit; -- busy
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err : slbit; -- error
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dout : slv16; -- data (output from slave)
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end record rb_sres_type;
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|
|
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constant rb_sres_init : rb_sres_type :=
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('0','0','0', -- ack, busy, err
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(others=>'0')); -- dout
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|
|
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component rri_core is -- rri, core interface
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component rlink_core is -- rlink core with 9bit iface
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generic (
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generic (
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ATOWIDTH : positive := 5; -- access timeout counter width
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ATOWIDTH : positive := 5; -- access timeout counter width
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ITOWIDTH : positive := 6); -- idle timeout counter width
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ITOWIDTH : positive := 6); -- idle timeout counter width
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_INT : in slbit := '0'; -- rri ito time unit clock enable
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CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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CP_DI : in slv9; -- comm port: data in
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RL_DI : in slv9; -- rlink 9b: data in
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CP_ENA : in slbit; -- comm port: data enable
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RL_ENA : in slbit; -- rlink 9b: data enable
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CP_BUSY : out slbit; -- comm port: data busy
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RL_BUSY : out slbit; -- rlink 9b: data busy
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CP_DO : out slv9; -- comm port: data out
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RL_DO : out slv9; -- rlink 9b: data out
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CP_VAL : out slbit; -- comm port: data valid
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RL_VAL : out slbit; -- rlink 9b: data valid
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CP_HOLD : in slbit; -- comm port: data hold
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RL_HOLD : in slbit; -- rlink 9b: data hold
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CP_FLUSH : out slbit; -- comm port: data flush
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RL_MONI : out rl_moni_type; -- rlink: monitor port
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16; -- rbus: look at me
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RB_LAM : in slv16; -- rbus: look at me
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RB_STAT : in slv3 -- rbus: status flags
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RB_STAT : in slv3 -- rbus: status flags
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);
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);
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end component;
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end component;
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|
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component rricp_aif is -- rri comm port, abstract interface
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component rlink_aif is -- rlink, abstract interface
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_INT : in slbit := '0'; -- rri ito time unit clock enable
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CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
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RESET : in slbit :='0'; -- reset
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RESET : in slbit :='0'; -- reset
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CP_DI : in slv9; -- comm port: data in
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RL_DI : in slv9; -- rlink 9b: data in
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CP_ENA : in slbit; -- comm port: data enable
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RL_ENA : in slbit; -- rlink 9b: data enable
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CP_BUSY : out slbit; -- comm port: data busy
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RL_BUSY : out slbit; -- rlink 9b: data busy
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CP_DO : out slv9; -- comm port: data out
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RL_DO : out slv9; -- rlink 9b: data out
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CP_VAL : out slbit; -- comm port: data valid
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RL_VAL : out slbit; -- rlink 9b: data valid
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CP_HOLD : in slbit := '0' -- comm port: data hold
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RL_HOLD : in slbit := '0' -- rlink 9b: data hold
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);
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);
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end component;
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end component;
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component rrirp_aif is -- rri reg port, abstract interface
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component rlink_rlb2rl is -- rlink 8 bit(rlb) to 9 bit(rl) adapter
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generic (
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CPREF : slv4 := c_rlink_cpref; -- comma prefix
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IFAWIDTH : natural := 5; -- input fifo address width (0=none)
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OFAWIDTH : natural := 5); -- output fifo address width (0=none)
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RLB_DI : in slv8; -- rlink 8b: data in
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RB_SRES : out rb_sres_type; -- rbus: response
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RLB_ENA : in slbit; -- rlink 8b: data enable
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RB_LAM : out slv16; -- rbus: look at me
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RLB_BUSY : out slbit; -- rlink 8b: data busy
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RB_STAT : out slv3 -- rbus: status flags
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RLB_DO : out slv8; -- rlink 8b: data out
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RLB_VAL : out slbit; -- rlink 8b: data valid
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RLB_HOLD : in slbit; -- rlink 8b: data hold
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IFIFO_SIZE : out slv4; -- input fifo size (4 msb's)
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OFIFO_SIZE : out slv4; -- output fifo fill (4 msb's)
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RL_DI : out slv9; -- rlink 9b: data in
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RL_ENA : out slbit; -- rlink 9b: data enable
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RL_BUSY : in slbit; -- rlink 9b: data busy
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RL_DO : in slv9; -- rlink 9b: data out
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RL_VAL : in slbit; -- rlink 9b: data valid
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RL_HOLD : out slbit -- rlink 9b: data hold
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);
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end component;
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|
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-- this definition logically belongs into the 'for test benches' section'
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-- must be here because it is needed as generic default in rlink_base
|
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-- simbus sb_cntl field usage for rlink
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constant sbcntl_sbf_rlmon : integer := 15;
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|
|
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component rlink_base is -- rlink base: core+rl2rlb+rlmon+rbmon
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-- with buffered 8bit interface
|
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generic (
|
|
ATOWIDTH : positive := 5; -- access timeout counter width
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|
ITOWIDTH : positive := 6; -- idle timeout counter width
|
|
CPREF : slv4 := c_rlink_cpref; -- comma prefix
|
|
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
|
|
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
|
|
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
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ENAPIN_RBMON : integer := sbcntl_sbf_rbmon); -- SB_CNTL for rbmon (-1=none)
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port (
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CLK : in slbit; -- clock
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CE_INT : in slbit := '0'; -- rlink ito time unit clock enable
|
|
RESET : in slbit; -- reset
|
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RLB_DI : in slv8; -- rlink 8b: data in
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RLB_ENA : in slbit; -- rlink 8b: data enable
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|
RLB_BUSY : out slbit; -- rlink 8b: data busy
|
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RLB_DO : out slv8; -- rlink 8b: data out
|
|
RLB_VAL : out slbit; -- rlink 8b: data valid
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RLB_HOLD : in slbit; -- rlink 8b: data hold
|
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IFIFO_SIZE : out slv4; -- input fifo size (4 msb's)
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OFIFO_SIZE : out slv4; -- output fifo fill (4 msb's)
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RL_MONI : out rl_moni_type; -- rlink: monitor port
|
|
RB_MREQ : out rb_mreq_type; -- rbus: request
|
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16; -- rbus: look at me
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RB_STAT : in slv3 -- rbus: status flags
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);
|
);
|
end component;
|
end component;
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|
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component rri_serport is -- rri serport adapter
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type rl_ser_moni_type is record -- rlink_serport monitor port
|
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rxerr : slbit; -- rx err
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rxdrop : slbit; -- rx drop
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rxact : slbit; -- rx active
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txact : slbit; -- tx active
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abact : slbit; -- ab active
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abdone : slbit; -- ab done
|
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clkdiv : slv16; -- clock divider
|
|
end record rl_ser_moni_type;
|
|
|
|
constant rl_ser_moni_init : rl_ser_moni_type :=
|
|
('0','0', -- rxerr,rxdrop
|
|
'0','0', -- rxact,txact
|
|
'0','0', -- abact,abdone
|
|
(others=>'0')); -- clkdiv
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|
|
|
constant c_rlink_serport_rbf_fena: integer := 12; --
|
|
subtype c_rlink_serport_rbf_fwidth is integer range 11 downto 9; --
|
|
subtype c_rlink_serport_rbf_fdelay is integer range 8 downto 6; --
|
|
subtype c_rlink_serport_rbf_rtsoff is integer range 5 downto 3; --
|
|
subtype c_rlink_serport_rbf_rtson is integer range 2 downto 0; --
|
|
|
|
component rlink_serport is -- rlink serport adapter
|
generic (
|
generic (
|
CPREF : slv4 := "1000"; -- comma prefix
|
RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8);
|
FAWIDTH : positive := 5; -- rx fifo address port width
|
|
CDWIDTH : positive := 13; -- clk divider width
|
CDWIDTH : positive := 13; -- clk divider width
|
CDINIT : natural := 15); -- clk divider initial/reset setting
|
CDINIT : natural := 15); -- clk divider initial/reset setting
|
port (
|
port (
|
CLK : in slbit; -- clock
|
CLK : in slbit; -- clock
|
CE_USEC : in slbit; -- 1 usec clock enable
|
CE_USEC : in slbit; -- 1 usec clock enable
|
| Line 156... |
Line 224... |
RESET : in slbit; -- reset
|
RESET : in slbit; -- reset
|
RXSD : in slbit; -- receive serial data (board view)
|
RXSD : in slbit; -- receive serial data (board view)
|
TXSD : out slbit; -- transmit serial data (board view)
|
TXSD : out slbit; -- transmit serial data (board view)
|
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
|
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
|
RTS_N : out slbit; -- request to send (act.low, board view)
|
RTS_N : out slbit; -- request to send (act.low, board view)
|
CP_DI : out slv9; -- comm port: data in
|
RLB_DI : out slv8; -- rlink 8b: data in
|
CP_ENA : out slbit; -- comm port: data enable
|
RLB_ENA : out slbit; -- rlink 8b: data enable
|
CP_BUSY : in slbit; -- comm port: data busy
|
RLB_BUSY : in slbit; -- rlink 8b: data busy
|
CP_DO : in slv9; -- comm port: data out
|
RLB_DO : in slv8; -- rlink 8b: data out
|
CP_VAL : in slbit; -- comm port: data valid
|
RLB_VAL : in slbit; -- rlink 8b: data valid
|
CP_HOLD : out slbit; -- comm port: data hold
|
RLB_HOLD : out slbit; -- rlink 8b: data hold
|
CP_FLUSH : in slbit := '0' -- comm port: data flush
|
RB_MREQ : in rb_mreq_type; -- rbus: request (for inits only)
|
|
IFIFO_SIZE : in slv4; -- rlink_rlb2rb: input fifo size
|
|
RL_MONI : in rl_moni_type; -- rlink_core: monitor port
|
|
RL_SER_MONI : out rl_ser_moni_type -- rlink_serport: monitor port
|
);
|
);
|
end component;
|
end component;
|
|
|
component rri_core_serport is -- rri, core+serport with cpmon+rbmon
|
component rlink_base_serport is -- rlink base+serport combo
|
generic (
|
generic (
|
ATOWIDTH : positive := 5; -- access timeout counter width
|
ATOWIDTH : positive := 5; -- access timeout counter width
|
ITOWIDTH : positive := 6; -- idle timeout counter width
|
ITOWIDTH : positive := 6; -- idle timeout counter width
|
FAWIDTH : positive := 5; -- rx fifo address port width
|
CPREF : slv4 := c_rlink_cpref; -- comma prefix
|
|
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
|
|
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
|
|
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
|
|
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
|
|
RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8);
|
CDWIDTH : positive := 13; -- clk divider width
|
CDWIDTH : positive := 13; -- clk divider width
|
CDINIT : natural := 15); -- clk divider initial/reset setting
|
CDINIT : natural := 15); -- clk divider initial/reset setting
|
port (
|
port (
|
CLK : in slbit; -- clock
|
CLK : in slbit; -- clock
|
CE_USEC : in slbit; -- 1 usec clock enable
|
CE_USEC : in slbit; -- 1 usec clock enable
|
| Line 186... |
Line 262... |
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
|
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
|
RTS_N : out slbit; -- request to send (act.low, board view)
|
RTS_N : out slbit; -- request to send (act.low, board view)
|
RB_MREQ : out rb_mreq_type; -- rbus: request
|
RB_MREQ : out rb_mreq_type; -- rbus: request
|
RB_SRES : in rb_sres_type; -- rbus: response
|
RB_SRES : in rb_sres_type; -- rbus: response
|
RB_LAM : in slv16; -- rbus: look at me
|
RB_LAM : in slv16; -- rbus: look at me
|
RB_STAT : in slv3 -- rbus: status flags
|
RB_STAT : in slv3; -- rbus: status flags
|
|
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
|
|
RL_SER_MONI : out rl_ser_moni_type -- rlink_serport: monitor port
|
);
|
);
|
end component;
|
end component;
|
|
|
component rb_sres_or_2 is -- rribus result or, 2 input
|
--
|
port (
|
-- components for use in test benches (not synthesizable)
|
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
|
--
|
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
|
|
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
|
|
);
|
|
end component;
|
|
component rb_sres_or_3 is -- rribus result or, 3 input
|
|
port (
|
|
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
|
|
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
|
|
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
|
|
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
|
|
);
|
|
end component;
|
|
component rb_sres_or_4 is -- rribus result or, 4 input
|
|
port (
|
|
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
|
|
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
|
|
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
|
|
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
|
|
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
|
|
);
|
|
end component;
|
|
|
|
component rri_wreg_rw_3 is -- rri: wide register r/w 3 bit select
|
component rlink_mon is -- rlink monitor
|
generic (
|
generic (
|
DWIDTH : positive := 16);
|
DWIDTH : positive := 9); -- data port width (8 or 9)
|
port (
|
port (
|
CLK : in slbit; -- clock
|
CLK : in slbit; -- clock
|
RESET : in slbit; -- reset
|
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
|
FADDR : slv3; -- field address
|
ENA : in slbit := '1'; -- enable monitor output
|
SEL : slbit; -- select
|
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
|
DATA : out slv(DWIDTH-1 downto 0); -- data
|
RL_ENA : in slbit; -- rlink: data enable
|
RB_MREQ : in rb_mreq_type; -- rribus request
|
RL_BUSY : in slbit; -- rlink: data busy
|
RB_SRES : out rb_sres_type -- rribus response
|
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
|
|
RL_VAL : in slbit; -- rlink: data valid
|
|
RL_HOLD : in slbit -- rlink: data hold
|
);
|
);
|
end component;
|
end component;
|
|
|
component rri_wreg_w_3 is -- rri: wide register w-o 3 bit select
|
component rlink_mon_sb is -- simbus wrap for rlink monitor
|
generic (
|
generic (
|
DWIDTH : positive := 16);
|
DWIDTH : positive := 9; -- data port width (8 or 9)
|
|
ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable
|
port (
|
port (
|
CLK : in slbit; -- clock
|
CLK : in slbit; -- clock
|
RESET : in slbit; -- reset
|
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
|
FADDR : slv3; -- field address
|
RL_ENA : in slbit; -- rlink: data enable
|
SEL : slbit; -- select
|
RL_BUSY : in slbit; -- rlink: data busy
|
DATA : out slv(DWIDTH-1 downto 0); -- data
|
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
|
RB_MREQ : in rb_mreq_type; -- rribus request
|
RL_VAL : in slbit; -- rlink: data valid
|
RB_SRES : out rb_sres_type -- rribus response
|
RL_HOLD : in slbit -- rlink: data hold
|
);
|
|
end component;
|
|
|
|
component rri_wreg_r_3 is -- rri: wide register r-o 3 bit select
|
|
generic (
|
|
DWIDTH : positive := 16);
|
|
port (
|
|
FADDR : slv3; -- field address
|
|
SEL : slbit; -- select
|
|
DATA : in slv(DWIDTH-1 downto 0); -- data
|
|
RB_SRES : out rb_sres_type -- rribus response
|
|
);
|
);
|
end component;
|
end component;
|
|
|
end rrilib;
|
end rlinklib;
|
|
|
No newline at end of file
|
No newline at end of file
|
