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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [vlib/] [rlink/] [tb/] [rlinktblib.vhd] - Diff between revs 2 and 8

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-- $Id: rritblib.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: rritblib.vhd 338 2010-11-13 22:19:25Z mueller $
--
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
--
-- This program is free software; you may redistribute and/or modify it under
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- the terms of the GNU General Public License as published by the Free
Line 14... Line 14...
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Package Name:   rritblib
-- Package Name:   rritblib
-- Description:    Remote Register Interface test environment components
-- Description:    Remote Register Interface test environment components
--
--
-- Dependencies:   -
-- Dependencies:   -
-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.29
-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History: 
-- Revision History: 
-- Date         Rev Version  Comment
-- Date         Rev Version  Comment
 
-- 2010-11-13   338   2.5.2  add rritb_core_dcm
-- 2010-06-26   309   2.5.1  add rritb_sres_or_mon
-- 2010-06-26   309   2.5.1  add rritb_sres_or_mon
-- 2010-06-06   302   2.5    use sop/eop framing instead of soc+chaining
-- 2010-06-06   302   2.5    use sop/eop framing instead of soc+chaining
-- 2010-06-05   301   2.1.2  renamed _rpmon -> _rbmon
-- 2010-06-05   301   2.1.2  renamed _rpmon -> _rbmon
-- 2010-05-02   287   2.1.1  rename CE_XSEC->CE_INT,RP_STAT->RB_STAT
-- 2010-05-02   287   2.1.1  rename CE_XSEC->CE_INT,RP_STAT->RB_STAT
--                           drop RP_IINT signal from interfaces
--                           drop RP_IINT signal from interfaces
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    RX_DATA : out slv8;                 -- read data         (data ext->tb)
    RX_DATA : out slv8;                 -- read data         (data ext->tb)
    RX_VAL : out slbit;                 -- read data valid   (data ext->tb)
    RX_VAL : out slbit;                 -- read data valid   (data ext->tb)
    RX_HOLD : in slbit;                 -- read data hold    (data ext->tb)
    RX_HOLD : in slbit;                 -- read data hold    (data ext->tb)
    TX_DATA : in slv8;                  -- write data        (data tb->ext)
    TX_DATA : in slv8;                  -- write data        (data tb->ext)
    TX_ENA : in slbit                   -- write data enable (data tb->ext)
    TX_ENA : in slbit                   -- write data enable (data tb->ext)
 
  );
 
end component;
 
 
 
component rritb_core_dcm is             -- dcm aware core of rri/cext based tb's
 
  generic (
 
    CLKOSC_PERIOD : time :=  20 ns;     -- clock osc period
 
    CLKOSC_OFFSET : time := 200 ns;     -- clock osc offset (time to start clk)
 
    SETUP_TIME : time :=   5 ns;        -- setup time
 
    C2OUT_TIME : time :=  10 ns);       -- clock to output time
 
  port (
 
    CLKOSC : out slbit;                 -- clock osc
 
    CLKSYS : in slbit;                  -- DCM derived system clock
 
    RX_DATA : out slv8;                 -- read data         (data ext->tb)
 
    RX_VAL : out slbit;                 -- read data valid   (data ext->tb)
 
    RX_HOLD : in slbit;                 -- read data hold    (data ext->tb)
 
    TX_DATA : in slv8;                  -- write data        (data tb->ext)
 
    TX_ENA : in slbit                   -- write data enable (data tb->ext)
  );
  );
end component;
end component;
 
 
component rricp_rp is                   -- rri comm->reg port aif forwarder
component rricp_rp is                   -- rri comm->reg port aif forwarder
                                        -- implements rricp_aif, uses rrirp_aif
                                        -- implements rricp_aif, uses rrirp_aif

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