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-- $Id: serport_uart_autobaud.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: serport_uart_autobaud.vhd 417 2011-10-22 10:30:29Z mueller $
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--
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Description: serial port UART - autobauder
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-- Description: serial port UART - autobauder
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: tb/tb_serport_autobaud
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-- Test bench: tb/tb_serport_autobaud
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
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-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-10-22 417 1.0.4 now numeric_std clean
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-- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding
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-- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding
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-- 2007-10-14 89 1.0.2 all instantiation with CDINIT=0
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-- 2007-10-14 89 1.0.2 all instantiation with CDINIT=0
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-30 62 1.0 Initial version
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-- 2007-06-30 62 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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entity serport_uart_autobaud is -- serial port uart: autobauder
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entity serport_uart_autobaud is -- serial port uart: autobauder
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generic (
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generic (
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-- gives the best rounded estimate of CLKDIV.
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-- gives the best rounded estimate of CLKDIV.
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-- - therefore ccnt is inititialized with 111111.101: 101 + 111 -> 1100
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-- - therefore ccnt is inititialized with 111111.101: 101 + 111 -> 1100
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-- --> ccntinit = -3
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-- --> ccntinit = -3
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constant ccntinit : slv(CDWIDTH-1+3 downto 0) :=
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constant ccntinit : slv(CDWIDTH-1+3 downto 0) :=
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conv_std_logic_vector(2**(CDWIDTH+3)-3, CDWIDTH+3);
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slv(to_unsigned(2**(CDWIDTH+3)-3, CDWIDTH+3));
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constant mcntzero : slv7 := (others=>'0');
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constant mcntzero : slv7 := (others=>'0');
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constant mcntlast : slv7 := (others=>'1');
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constant mcntlast : slv7 := (others=>'1');
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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conv_std_logic_vector(CDINIT,CDWIDTH)&"000",
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slv(to_unsigned(CDINIT,CDWIDTH))&"000",
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(others=>'0'),
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(others=>'0'),
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'0',
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'0',
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s_idle
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s_idle
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);
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);
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severity FAILURE;
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severity FAILURE;
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if CLK'event and CLK='1' then
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if rising_edge(CLK) then
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if RESET = '1' then
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if RESET = '1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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case r.state is
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case r.state is
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when s_idle => -- s_idle: idle, detect break --------
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when s_idle => -- s_idle: idle, detect break --------
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iact := '0';
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iact := '0';
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if CE_MSEC = '1' then -- if end of msec
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if CE_MSEC = '1' then -- if end of msec
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if r.seen1 = '0' then -- if no '1' seen on RXD
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if r.seen1 = '0' then -- if no '1' seen on RXD
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n.mcnt := unsigned(r.mcnt) + 1; -- up break timer counter
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n.mcnt := slv(unsigned(r.mcnt) + 1); -- up break timer counter
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if r.mcnt = mcntlast then -- after 127 msec
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if r.mcnt = mcntlast then -- after 127 msec
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n.state := s_break; -- break detected !
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n.state := s_break; -- break detected !
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end if;
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end if;
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else -- otherwise if '1' seen
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else -- otherwise if '1' seen
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n.mcnt := mcntzero; -- clear break timer again
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n.mcnt := mcntzero; -- clear break timer again
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when s_sync => -- s_sync: wait for end of '0' bits --
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when s_sync => -- s_sync: wait for end of '0' bits --
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if RXSD = '1' then -- if end of '0' bits seen
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if RXSD = '1' then -- if end of '0' bits seen
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n.state := s_idle; -- to s_idle, autobauding done
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n.state := s_idle; -- to s_idle, autobauding done
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idone := '1'; -- emit done pulse
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idone := '1'; -- emit done pulse
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else -- otherwise still in '0' of sync
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else -- otherwise still in '0' of sync
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n.ccnt := unsigned(n.ccnt) + 1; -- increment ccnt
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n.ccnt := slv(unsigned(n.ccnt) + 1); -- increment ccnt
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end if;
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end if;
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when others => null; -- -----------------------------------
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when others => null; -- -----------------------------------
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end case;
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end case;
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