| Line 1... |
Line 1... |
-- $Id: tb_serport_uart_rx.vhd 417 2011-10-22 10:30:29Z mueller $
|
-- $Id: tb_serport_uart_rx.vhd 444 2011-12-25 10:04:58Z mueller $
|
--
|
--
|
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
--
|
--
|
-- This program is free software; you may redistribute and/or modify it under
|
-- This program is free software; you may redistribute and/or modify it under
|
-- the terms of the GNU General Public License as published by the Free
|
-- the terms of the GNU General Public License as published by the Free
|
| Line 14... |
Line 14... |
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
-- Module Name: tb_serport_uart_rx - sim
|
-- Module Name: tb_serport_uart_rx - sim
|
-- Description: Test bench for serport_uart_rx
|
-- Description: Test bench for serport_uart_rx
|
--
|
--
|
-- Dependencies: simlib/simclk
|
-- Dependencies: simlib/simclk
|
|
-- simlib/simclkcnt
|
-- tbd_serport_uart_rx [UUT]
|
-- tbd_serport_uart_rx [UUT]
|
--
|
--
|
-- To test: serport_uart_rx
|
-- To test: serport_uart_rx
|
--
|
--
|
-- Target Devices: generic
|
-- Target Devices: generic
|
| Line 28... |
Line 29... |
-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (63488 cl 15.21s)
|
-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (63488 cl 15.21s)
|
-- 2007-10-21 91 - 0.26 - - c:ok (63488 cl 7.12s)
|
-- 2007-10-21 91 - 0.26 - - c:ok (63488 cl 7.12s)
|
--
|
--
|
-- Revision History:
|
-- Revision History:
|
-- Date Rev Version Comment
|
-- Date Rev Version Comment
|
|
-- 2011-12-23 444 1.1 use new simclk/simclkcnt
|
-- 2011-10-22 417 1.0.3 now numeric_std clean
|
-- 2011-10-22 417 1.0.3 now numeric_std clean
|
-- 2010-04-24 281 1.0.2 use direct instatiation for tbd_
|
-- 2010-04-24 281 1.0.2 use direct instatiation for tbd_
|
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
|
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
|
-- 2007-10-21 91 1.0 Initial version
|
-- 2007-10-21 91 1.0 Initial version
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
| Line 59... |
Line 61... |
signal RXVAL : slbit := '0';
|
signal RXVAL : slbit := '0';
|
signal RXERR : slbit := '0';
|
signal RXERR : slbit := '0';
|
signal RXACT : slbit := '0';
|
signal RXACT : slbit := '0';
|
|
|
signal CLK_STOP : slbit := '0';
|
signal CLK_STOP : slbit := '0';
|
signal CLK_CYCLE : slv31 := (others=>'0');
|
signal CLK_CYCLE : integer := 0;
|
|
|
signal N_MON_VAL : slbit := '0';
|
signal N_MON_VAL : slbit := '0';
|
signal N_MON_ERR : slbit := '0';
|
signal N_MON_ERR : slbit := '0';
|
signal N_MON_DAT : slv8 := (others=>'0');
|
signal N_MON_DAT : slv8 := (others=>'0');
|
signal R_MON_VAL_1 : slbit := '0';
|
signal R_MON_VAL_1 : slbit := '0';
|
| Line 78... |
Line 80... |
constant setup_time : time := 5 ns;
|
constant setup_time : time := 5 ns;
|
constant c2out_time : time := 10 ns;
|
constant c2out_time : time := 10 ns;
|
|
|
begin
|
begin
|
|
|
SYSCLK : simclk
|
CLKGEN : simclk
|
generic map (
|
generic map (
|
PERIOD => clock_period,
|
PERIOD => clock_period,
|
OFFSET => clock_offset)
|
OFFSET => clock_offset)
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
CLK_CYCLE => CLK_CYCLE,
|
|
CLK_STOP => CLK_STOP
|
CLK_STOP => CLK_STOP
|
);
|
);
|
|
|
|
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
|
|
|
UUT : entity work.tbd_serport_uart_rx
|
UUT : entity work.tbd_serport_uart_rx
|
port map (
|
port map (
|
CLK => CLK,
|
CLK => CLK,
|
RESET => RESET,
|
RESET => RESET,
|
CLKDIV => CLKDIV,
|
CLKDIV => CLKDIV,
|
