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-- $Id: tb_serport_uart_rxtx.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: tb_serport_uart_rxtx.vhd 417 2011-10-22 10:30:29Z mueller $
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--
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
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-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
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-- 2007-10-12 88 - 0.26 - - c:ok
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-- 2007-10-12 88 - 0.26 - - c:ok
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-10-22 417 1.1.3 now numeric_std clean
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-- 2010-04-24 281 1.1.2 use direct instatiation for tbd_
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-- 2010-04-24 281 1.1.2 use direct instatiation for tbd_
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-- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits
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-- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits
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-- 2007-10-21 91 1.1 now use 'send' command, self-checking (FAIL's)
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-- 2007-10-21 91 1.1 now use 'send' command, self-checking (FAIL's)
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-08-27 76 1.0 Initial version
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-- 2007-08-27 76 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.simlib.all;
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use work.simlib.all;
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architecture sim of tb_serport_uart_rxtx is
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architecture sim of tb_serport_uart_rxtx is
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signal CLK : slbit := '0';
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signal CLK : slbit := '0';
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signal RESET : slbit := '0';
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signal RESET : slbit := '0';
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signal CLKDIV : slv13 := conv_std_logic_vector(15, 13);
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signal CLKDIV : slv13 := slv(to_unsigned(15, 13));
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signal RXDATA : slv8 := (others=>'0');
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signal RXDATA : slv8 := (others=>'0');
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signal RXVAL : slbit := '0';
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signal RXVAL : slbit := '0';
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signal RXERR : slbit := '0';
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signal RXERR : slbit := '0';
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signal RXACT : slbit := '0';
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signal RXACT : slbit := '0';
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signal TXSD : slbit := '0';
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signal TXSD : slbit := '0';
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read_ea(iline, idelta);
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read_ea(iline, idelta);
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wait for idelta*clock_period;
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wait for idelta*clock_period;
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when ".rate " => -- .rate
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when ".rate " => -- .rate
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read_ea(iline, irate);
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read_ea(iline, irate);
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CLKDIV <= conv_std_logic_vector(irate-1, 13);
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CLKDIV <= slv(to_unsigned(irate-1, 13));
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when "send " => -- send
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when "send " => -- send
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read_ea(iline, idelta);
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read_ea(iline, idelta);
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read_ea(iline, itxdata);
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read_ea(iline, itxdata);
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proc_moni: process
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proc_moni: process
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variable oline : line;
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variable oline : line;
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begin
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begin
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loop
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loop
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wait until CLK'event and CLK='1';
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wait until rising_edge(CLK);
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if R_MON_VAL_1 = '1' then
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if R_MON_VAL_1 = '1' then
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if R_MON_VAL_2 = '1' then
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if R_MON_VAL_2 = '1' then
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writetimestamp(oline, CLK_CYCLE, ": moni ");
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writetimestamp(oline, CLK_CYCLE, ": moni ");
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write(oline, string'(" FAIL MISSING DATA="));
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write(oline, string'(" FAIL MISSING DATA="));
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