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-- $Id: simlib.vhd 427 2011-11-19 21:04:11Z mueller $
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-- $Id: simlib.vhd 444 2011-12-25 10:04:58Z mueller $
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--
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--
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-12-23 444 2.0 drop CLK_CYCLE from simclk,simclkv; use integer for
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-- simclkcnt(CLK_CYCLE),writetimestamp(clkcyc);
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-- 2011-11-18 427 1.3.8 now numeric_std clean
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-- 2011-11-18 427 1.3.8 now numeric_std clean
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-- 2010-12-22 346 1.3.7 rename readcommand -> readdotcomm
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-- 2010-12-22 346 1.3.7 rename readcommand -> readdotcomm
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-- 2010-11-13 338 1.3.6 add simclkcnt; xx.x ns time in writetimestamp()
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-- 2010-11-13 338 1.3.6 add simclkcnt; xx.x ns time in writetimestamp()
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-- 2008-03-24 129 1.3.5 CLK_CYCLE now 31 bits
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-- 2008-03-24 129 1.3.5 CLK_CYCLE now 31 bits
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-- 2008-03-02 121 1.3.4 added readempty (to discard rest of line)
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-- 2008-03-02 121 1.3.4 added readempty (to discard rest of line)
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field: in width:=0; -- field width
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field: in width:=0; -- field width
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base: in integer:= 2); -- default base
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base: in integer:= 2); -- default base
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procedure writetimestamp(
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procedure writetimestamp(
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L: inout line;
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L: inout line;
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clkcyc: in slv31;
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clkcyc: in integer;
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str : in string := null_string);
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str : in string := null_string);
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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component simclk is -- test bench clock generator
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component simclk is -- test bench clock generator
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generic (
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generic (
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PERIOD : time := 20 ns; -- clock period
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PERIOD : time := 20 ns; -- clock period
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OFFSET : time := 200 ns); -- clock offset (first up transition)
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OFFSET : time := 200 ns); -- clock offset (first up transition)
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port (
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port (
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CLK : out slbit; -- clock
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CLK : out slbit; -- clock
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CLK_CYCLE : out slv31; -- clock cycle number
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CLK_STOP : in slbit -- clock stop trigger
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CLK_STOP : in slbit -- clock stop trigger
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);
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);
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end component;
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end component;
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component simclkv is -- test bench clock generator
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component simclkv is -- test bench clock generator
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-- with variable periods
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-- with variable periods
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port (
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port (
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CLK : out slbit; -- clock
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CLK : out slbit; -- clock
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CLK_CYCLE : out slv31; -- clock cycle number
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CLK_PERIOD : in time; -- clock period
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CLK_PERIOD : in time; -- clock period
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CLK_HOLD : in slbit; -- if 1, hold clocks in 0 state
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CLK_HOLD : in slbit; -- if 1, hold clocks in 0 state
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CLK_STOP : in slbit -- clock stop trigger
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CLK_STOP : in slbit -- clock stop trigger
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);
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);
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end component;
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end component;
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component simclkcnt is -- test bench system clock cycle counter
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component simclkcnt is -- test bench system clock cycle counter
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CLK_CYCLE : out slv31 -- clock cycle number
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CLK_CYCLE : out integer -- clock cycle number
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);
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);
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end component;
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end component;
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end package simlib;
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end package simlib;
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-- -------------------------------------
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-- -------------------------------------
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procedure writetimestamp(
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procedure writetimestamp(
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L: inout line;
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L: inout line;
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clkcyc: in slv31;
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clkcyc: in integer;
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str: in string := null_string) is
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str: in string := null_string) is
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variable t_nsec : integer := 0;
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variable t_nsec : integer := 0;
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variable t_psec : integer := 0;
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variable t_psec : integer := 0;
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variable t_dnsec : integer := 0;
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variable t_dnsec : integer := 0;
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write(L, t_nsec, right, 8);
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write(L, t_nsec, right, 8);
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write(L,'.');
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write(L,'.');
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write(L, t_dnsec, right, 1);
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write(L, t_dnsec, right, 1);
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write(L, string'(" ns"));
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write(L, string'(" ns"));
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write(L, to_integer(unsigned(clkcyc)), right, 7);
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write(L, clkcyc, right, 7);
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if str /= null_string then
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if str /= null_string then
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write(L, str);
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write(L, str);
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end if;
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end if;
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end procedure writetimestamp;
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end procedure writetimestamp;
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