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-- $Id: xlib.vhd 432 2011-11-25 20:16:28Z mueller $
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-- $Id: xlib.vhd 538 2013-10-06 17:21:25Z mueller $
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--
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Package Name: xlib
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-- Package Name: xlib
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-- Description: Xilinx specific components
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-- Description: Xilinx specific components
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1, 14.5, 14.6; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2013-10-06 538 1.0.10 add s6_cmt_sfs
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-- 2013-09-28 535 1.0.9 add s7_cmt_sfs
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-- 2011-11-24 432 1.0.8 add iob_oddr2_simple
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-- 2011-11-24 432 1.0.8 add iob_oddr2_simple
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-- 2011-11-17 426 1.0.7 rename dcm_sp_sfs -> dcm_sfs; remove family generic
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-- 2011-11-17 426 1.0.7 rename dcm_sp_sfs -> dcm_sfs; remove family generic
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-- 2011-11-10 423 1.0.6 add family generic for dcm_sp_sfs
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-- 2011-11-10 423 1.0.6 add family generic for dcm_sp_sfs
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-- 2010-11-07 337 1.0.5 add dcm_sp_sfs
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-- 2010-11-07 337 1.0.5 add dcm_sp_sfs
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-- 2008-05-23 149 1.0.4 add iob_io(_gen)
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-- 2008-05-23 149 1.0.4 add iob_io(_gen)
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end component;
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end component;
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component dcm_sfs is -- DCM for simple frequency synthesis
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component dcm_sfs is -- DCM for simple frequency synthesis
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generic (
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generic (
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CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32)
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CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32)
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CLKFX_MULTIPLY : positive := 2; -- FX clock divide (2-32)
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CLKFX_MULTIPLY : positive := 2; -- FX clock multiply (2-32) (1->no DCM)
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CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
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CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
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port (
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port (
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CLKIN : in slbit; -- clock input
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CLKIN : in slbit; -- clock input
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CLKFX : out slbit; -- clock output (synthesized freq.)
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CLKFX : out slbit; -- clock output (synthesized freq.)
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LOCKED : out slbit -- dcm locked
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LOCKED : out slbit -- dcm locked
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);
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);
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end component;
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end component;
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component s7_cmt_sfs is -- 7-Series CMT for simple freq. synth.
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generic (
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VCO_DIVIDE : positive := 1; -- vco clock divide
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VCO_MULTIPLY : positive := 1; -- vco clock multiply
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OUT_DIVIDE : positive := 1; -- output divide
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CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
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CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
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STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
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GEN_TYPE : string := "PLL"); -- PLL or MMCM
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port (
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CLKIN : in slbit; -- clock input
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CLKFX : out slbit; -- clock output (synthesized freq.)
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LOCKED : out slbit -- pll/mmcm locked
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);
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end component;
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component s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
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generic (
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VCO_DIVIDE : positive := 1; -- vco clock divide
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VCO_MULTIPLY : positive := 1; -- vco clock multiply
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OUT_DIVIDE : positive := 1; -- output divide
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CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
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CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
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STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
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GEN_TYPE : string := "PLL"); -- PLL or DCM
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port (
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CLKIN : in slbit; -- clock input
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CLKFX : out slbit; -- clock output (synthesized freq.)
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LOCKED : out slbit -- pll/mmcm locked
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);
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end component;
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end package xlib;
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end package xlib;
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