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-- $Id: pdp11_munit.vhd 330 2010-09-19 17:43:53Z mueller $
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-- $Id: pdp11_munit.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Description: pdp11: mul/div unit for data (munit)
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-- Description: pdp11: mul/div unit for data (munit)
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.1.1 now numeric_std clean
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-- 2010-09-18 300 1.1 renamed from mbox
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-- 2010-09-18 300 1.1 renamed from mbox
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.pdp11.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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begin
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begin
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if CLK'event and CLK='1' then
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if rising_edge(CLK) then
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R_DD_L <= NEXT_DD_L;
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R_DD_L <= NEXT_DD_L;
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R_DDO_LT <= NEXT_DDO_LT;
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R_DDO_LT <= NEXT_DDO_LT;
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R_DIV_V <= NEXT_DIV_V;
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R_DIV_V <= NEXT_DIV_V;
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R_SHC <= NEXT_SHC;
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R_SHC <= NEXT_SHC;
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R_C1 <= NEXT_C1;
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R_C1 <= NEXT_C1;
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NEXT_C1 <= '1';
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NEXT_C1 <= '1';
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end if;
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end if;
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if S_DIV_CN='1' or S_ASH_CN='1' or S_ASHC_CN='1' then
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if S_DIV_CN='1' or S_ASH_CN='1' or S_ASHC_CN='1' then
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if R_SHC(5) = '0' then
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if R_SHC(5) = '0' then
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NEXT_SHC <= unsigned(R_SHC) - 1;
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NEXT_SHC <= slv(unsigned(R_SHC) - 1);
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else
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else
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NEXT_SHC <= unsigned(R_SHC) + 1;
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NEXT_SHC <= slv(unsigned(R_SHC) + 1);
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end if;
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end if;
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NEXT_C1 <= '0';
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NEXT_C1 <= '0';
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end if;
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end if;
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SHC_TC_L <= '0';
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SHC_TC_L <= '0';
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else
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else
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subadd := Q(0);
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subadd := Q(0);
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end if;
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end if;
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if subadd = '0' then
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if subadd = '0' then
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dd_h_new := signed(dd_h_old) + signed(DR);
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dd_h_new := slv(signed(dd_h_old) + signed(DR));
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else
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else
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dd_h_new := signed(dd_h_old) - signed(DR);
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dd_h_new := slv(signed(dd_h_old) - signed(DR));
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end if;
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end if;
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dd_gt := '0';
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dd_gt := '0';
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if dd_h_new(15) = '0' and
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if dd_h_new(15) = '0' and
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(unsigned(dd_h_new(14 downto 0))/=0 or
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(unsigned(dd_h_new(14 downto 0))/=0 or
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variable mul_c : slbit := '0';
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variable mul_c : slbit := '0';
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begin
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begin
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prod := signed(DSRC) * signed(DDST);
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prod := slv(signed(DSRC) * signed(DDST));
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case FUNC is
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case FUNC is
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when c_munit_func_mul =>
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when c_munit_func_mul =>
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omux_sel := "00";
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omux_sel := "00";
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when c_munit_func_div =>
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when c_munit_func_div =>
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