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# $Id: README.txt 434 2011-12-02 19:17:38Z mueller $
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# $Id: README.txt 442 2011-12-23 10:03:28Z mueller $
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Release notes for w11a
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Release notes for w11a
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Table of content:
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Table of content:
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2. Files ---------------------------------------------------------------------
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2. Files ---------------------------------------------------------------------
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doc Documentation
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doc Documentation
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rtl VHDL sources
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rtl VHDL sources
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rtl/bplib - board and component support libs
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rtl/bplib - board and component support libs
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rtl/bplib/atlys - for Digilent Atlys board
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rtl/bplib/issi - for ISSI parts
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rtl/bplib/issi - for ISSI parts
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rtl/bplib/micron - for Micron parts
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rtl/bplib/micron - for Micron parts
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rtl/bplib/nexys2 - for Digilent Nexsy2 board
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rtl/bplib/nexys2 - for Digilent Nexsy2 board
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rtl/bplib/nexys3 - for Digilent Nexsy3 board
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rtl/bplib/nexys3 - for Digilent Nexsy3 board
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rtl/bplib/nxcramlib - for CRAM part used in Nexys2/3
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rtl/bplib/s3board - for Digilent S3BOARD
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rtl/bplib/s3board - for Digilent S3BOARD
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rtl/ibus - ibus devices (UNIBUS peripherals)
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rtl/ibus - ibus devices (UNIBUS peripherals)
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rtl/sys_gen - top level designs
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rtl/sys_gen - top level designs
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rtl/sys_gen/tst_rlink - top level designs for an rlink tester
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rtl/sys_gen/tst_rlink - top level designs for an rlink tester
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rtl/sys_gen/tst_rlink/nexys2 - rlink tester system for Digilent Nexsy2
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nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3BOARD
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rtl/sys_gen/tst_rlink/nexys3 - rlink tester system for Digilent Nexsy3
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rtl/sys_gen/tst_serloop - top level designs for serport loop tester
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nexys2,nexys3,s3board - systems for Nexsy2,Nexsy3,S3BOARD
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rtl/sys_gen/tst_snhumanio - top level designs for human I/O tester
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atlys,nexys2,nexys3,s3board - systems for Atlys,Nexsy2,Nexsy3,S3BOARD
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rtl/sys_gen/w11a - top level designs for w11a SoC
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rtl/sys_gen/w11a - top level designs for w11a SoC
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rtl/sys_gen/w11a/nexys2 - w11a SoC for Digilent Nexsy2
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nexys2,nexys3,s3board - w11a systems for Nexsy2,Nexsy3,S3BOARD
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rtl/sys_gen/w11a/nexys3 - w11a SoC for Digilent Nexsy3
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rtl/sys_gen/w11a/s3board - w11a SoC for Digilent S3BOARD
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rtl/vlib - VHDL component libs
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rtl/vlib - VHDL component libs
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rtl/vlib/comlib - communication
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rtl/vlib/comlib - communication
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rtl/vlib/genlib - general
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rtl/vlib/genlib - general
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rtl/vlib/memlib - memory
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rtl/vlib/memlib - memory
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rtl/vlib/rbus - rri: rbus
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rtl/vlib/rbus - rri: rbus
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tools/src/librutiltpp - Tcl support commands implemented in C++
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tools/src/librutiltpp - Tcl support commands implemented in C++
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tools/tcl - Tcl scripts
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tools/tcl - Tcl scripts
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3. Change Log ----------------------------------------------------------------
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3. Change Log ----------------------------------------------------------------
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- trunk (2011-12-04: svn rev 15(oc) 436(wfjm); untagged w11a_V0.54) +++++++++
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- trunk (2011-12-23: svn rev 16(oc) 442(wfjm); untagged w11a_V0.55) +++++++++
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- Summary
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- Summary
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- added support for nexys3 board for w11a
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- added xon/xoff (software flow control) support to serport library
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- added test systems for serport verification
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- use new serport stack in sys_w11a_* and sys_tst_rlink_* systems
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- Changes
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- retired modules
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- vlib/rlink
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- rlink_rlb2rl - obsolete, now all in rlink_core8
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- rlink_base - use now new rlink_core8
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- rlink_serport - obsolete, now all in rlink_sp1c
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- rlink_base_serport - use now new rlink_sp1c
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- New features
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- New features
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- new modules
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- vlib/serport
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- serport_xonrx - xon/xoff logic rx path
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- serport_xontx - xon/xoff logic tx path
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- serport_1clock - serial port module (uart, fifo, flow control)
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- vlib/rlink
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- rlink_core8 - rlink core8 with 8bit interface
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- rlink_sp1c - rlink_core8 + serport_1clock combo
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- new unit tests
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- bplib/s3board/tb/tb_s3_sram_memctl (for s3board sram controller
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- bplib/nxcramlib/tb/tb_nx_cram_memctl_as (for nexys2,3 cram controller)
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- new systems
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- new systems
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- sys_gen/w11a/sys_w11a_n3
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- sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2
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- sys_gen/w11a/sys_tst_rlink_n3
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- sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3
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- sys_gen/tst_serloop/s3board/sys_tst_serloop1_s3
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- sys_gen/tst_rlink/s3board/sys_tst_rlink_s3
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- trunk (2011-12-04: svn rev 15(oc) 436(wfjm); untagged w11a_V0.54) +++++++++
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- Summary
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- added support for nexys3 board for w11a
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- Changes
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- Changes
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- module renames:
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- module renames:
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bplib/nexys2/n2_cram_dummy -> bplib/nxcramlib/nx_cram_dummy
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bplib/nexys2/n2_cram_dummy -> bplib/nxcramlib/nx_cram_dummy
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bplib/nexys2/n2_cram_memctl_as -> bplib/nxcramlib/nx_cram_memctl_as
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bplib/nexys2/n2_cram_memctl_as -> bplib/nxcramlib/nx_cram_memctl_as
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- New features
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- new systems
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- sys_gen/w11a/nexys3/sys_w11a_n3
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- sys_gen/w11a/nexys3/sys_tst_rlink_n3
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- Bug fixes
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- Bug fixes
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- tools/src/lib*: backend libraries compile now on 64 bit systems
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- tools/src/lib*: backend libraries compile now on 64 bit systems
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- trunk (2011-11-20: svn rev 14(oc) 428(wfjm); untagged w11a_V0.532) +++++++++
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- trunk (2011-11-20: svn rev 14(oc) 428(wfjm); untagged w11a_V0.532) +++++++++
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- Summary
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- Summary
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- generalized the 'human I/O' interface for s3board,nexys2/3 and atlys
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- generalized the 'human I/O' interface for s3board,nexys2/3 and atlys
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- added test design for the 'human I/O' interface
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- added test design for the 'human I/O' interface
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- no functional change of w11a CPU core or any existing test systems
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- no functional change of w11a CPU core or any existing test systems
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- New features
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- new modules
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- rtl/sys_gen/tst_snhumanio
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- sub-tree with test design for 'human I/O' interface modules
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- atlys, nexys2, and s3board directories contain the systems
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for the respectice Digilent boards
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- Changes
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- Changes
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- functional changes
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- functional changes
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- use now 'a6' polynomial of Koopman et al for crc8 in rlink
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- use now 'a6' polynomial of Koopman et al for crc8 in rlink
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- with one exception all vhdl sources use now numeric_std
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- with one exception all vhdl sources use now numeric_std
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- module renames:
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- module renames:
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vlib/xlib/dcm_sp_sfs_gsim -> vlib/xlib/dcm_sfs_gsim
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vlib/xlib/dcm_sp_sfs_gsim -> vlib/xlib/dcm_sfs_gsim
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vlib/xlib/dcm_sp_sfs_unisim -> vlib/xlib/dcm_sfs_unisim_s3e
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vlib/xlib/dcm_sp_sfs_unisim -> vlib/xlib/dcm_sfs_unisim_s3e
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vlib/xlib/tb/tb_dcm_sp_sfs -> vlib/xlib/tb/tb_dcm_sfs
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vlib/xlib/tb/tb_dcm_sp_sfs -> vlib/xlib/tb/tb_dcm_sfs
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- New features
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- new modules
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- rtl/sys_gen/tst_snhumanio
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- sub-tree with test design for 'human I/O' interface modules
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- atlys, nexys2, and s3board directories contain the systems
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for the respective Digilent boards
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- trunk (2011-09-11: svn rev 12(oc) 409(wfjm); untagged w11a_V0.531) +++++++++
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- trunk (2011-09-11: svn rev 12(oc) 409(wfjm); untagged w11a_V0.531) +++++++++
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- Summary
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- Summary
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- Many small changes to prepare upcoming support for
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- Many small changes to prepare upcoming support for
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- Spartan-6 boards (nexys3 and atlys)
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- Spartan-6 boards (nexys3 and atlys)
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- trunk (2011-04-17: svn rev 11(oc) 376(wfjm); untagged w11a_V0.53) ++++++++++
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- trunk (2011-04-17: svn rev 11(oc) 376(wfjm); untagged w11a_V0.53) ++++++++++
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- Summary
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- Summary
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- Introduce C++ and Tcl based backend server. A set of C++ classes provide
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- Introduce C++ and Tcl based backend server. A set of C++ classes provide
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the basic rlink communication promitives. Additional glue classes provide
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the basic rlink communication primitives. Additional glue classes provide
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a Tcl binding. This first phase contains the basic functionality needed
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a Tcl binding. This first phase contains the basic functionality needed
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to control simple test benches.
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to control simple test benches.
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- add an 'rlink exerciser' (tst_rlink) and a top level design for a Nexys2
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- add an 'rlink exerciser' (tst_rlink) and a top level design for a Nexys2
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board (sys_tst_rlink_n2) and a test suite implemented in Tcl.
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board (sys_tst_rlink_n2) and a test suite implemented in Tcl.
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ccrc -> cerr - indicates cmd crc error or other cmd level abort
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ccrc -> cerr - indicates cmd crc error or other cmd level abort
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dcrc -> derr - indicates data crc error or other data level abort
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dcrc -> derr - indicates data crc error or other data level abort
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ioto -> rbnak - indicates rbus abort, either no ack or timeout
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ioto -> rbnak - indicates rbus abort, either no ack or timeout
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ioerr -> rberr - indicates that rbus err flag was set
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ioerr -> rberr - indicates that rbus err flag was set
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- migrate to rbus protocol verion 3
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- migrate to rbus protocol version 3
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- in rb_mreq use now aval,re,we instead of req,we
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- in rb_mreq use now aval,re,we instead of req,we
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- basic rbus transaction now takes 2 cycles, one for address select, one
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- basic rbus transaction now takes 2 cycles, one for address select, one
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for data exchange. Same concept and reasoning behind as in ibus V2.
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for data exchange. Same concept and reasoning behind as in ibus V2.
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- vlib/rlink/rlink_core
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- vlib/rlink/rlink_core
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- signal renames:
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- signal renames:
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- renamed RRI_LAM -> RB_LAM in all ibus devices
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- renamed RRI_LAM -> RB_LAM in all ibus devices
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- renamed CLK -> I_CLK50 in all top level nexys2 and s3board designs
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- renamed CLK -> I_CLK50 in all top level nexys2 and s3board designs
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- migrate to ibus protocol verion 2
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- migrate to ibus protocol version 2
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- in ib_mreq use now aval,re,we,rmw instead of req,we,dip
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- in ib_mreq use now aval,re,we,rmw instead of req,we,dip
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- basic ibus transaction now takes 2 cycles, one for address select, one
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- basic ibus transaction now takes 2 cycles, one for address select, one
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for data exchange. This avoids too long logic paths in the ibus logic.
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for data exchange. This avoids too long logic paths in the ibus logic.
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- New features
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- New features
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