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-- $Id: ibdr_lp11.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: ibdr_lp11.vhd 335 2010-10-24 22:24:23Z mueller $
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--
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--
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-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Description: ibus dev(rem): LP11
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-- Description: ibus dev(rem): LP11
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-10-17 333 12.1 M53 xc3s1000-4 12 35 0 24 s 5.6
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-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 11 30 0 19 s 5.8
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-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 11 30 0 19 s 5.8
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
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-- 2010-10-17 333 1.2 use ibus V2 interface
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2009-06-21 228 1.0.1 generate interrupt locally when err=1
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-- 2009-06-21 228 1.0.1 generate interrupt locally when err=1
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-- 2009-05-30 220 1.0 Initial version
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-- 2009-05-30 220 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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-- fixed address: 177514
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-- fixed address: 177514
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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BRESET : in slbit; -- ibus reset
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RRI_LAM : out slbit; -- remote attention
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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EI_ACK : in slbit -- interrupt acknowledge
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);
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);
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constant csr_ibf_done : integer := 7;
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constant csr_ibf_done : integer := 7;
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constant csr_ibf_ie : integer := 6;
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constant csr_ibf_ie : integer := 6;
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constant buf_ibf_val : integer := 8;
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constant buf_ibf_val : integer := 8;
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type regs_type is record -- state registers
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type regs_type is record -- state registers
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ibsel : slbit; -- ibus select
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err : slbit; -- csr: error flag
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err : slbit; -- csr: error flag
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done : slbit; -- csr: done flag
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done : slbit; -- csr: done flag
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ie : slbit; -- csr: interrupt enable
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ie : slbit; -- csr: interrupt enable
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buf : slv7; -- buf:
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buf : slv7; -- buf:
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intreq : slbit; -- interrupt request
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intreq : slbit; -- interrupt request
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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'0', -- ibsel
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'1', -- err !! is set !!
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'1', -- err !! is set !!
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'1', -- done !! is set !!
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'1', -- done !! is set !!
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'0', -- ie
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'0', -- ie
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(others=>'0'), -- buf
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(others=>'0'), -- buf
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'0' -- intreq
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'0' -- intreq
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end process proc_regs;
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end process proc_regs;
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proc_next : process (R_REGS, IB_MREQ, EI_ACK)
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proc_next : process (R_REGS, IB_MREQ, EI_ACK)
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable ibsel : slbit := '0';
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variable idout : slv16 := (others=>'0');
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variable idout : slv16 := (others=>'0');
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variable ibreq : slbit := '0';
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variable ibrd : slbit := '0';
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variable ibrd : slbit := '0';
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variable ibw0 : slbit := '0';
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variable ibw0 : slbit := '0';
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variable ilam : slbit := '0';
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variable ilam : slbit := '0';
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begin
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begin
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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ibsel := '0';
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idout := (others=>'0');
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idout := (others=>'0');
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ibrd := not IB_MREQ.we;
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ibreq := IB_MREQ.re or IB_MREQ.we;
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ibrd := IB_MREQ.re;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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ilam := '0';
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ilam := '0';
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-- ibus address decoder
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-- ibus address decoder
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if IB_MREQ.req='1' and
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n.ibsel := '0';
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if IB_MREQ.aval='1' and
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IB_MREQ.addr(12 downto 2)=ibaddr_lp11(12 downto 2) then
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IB_MREQ.addr(12 downto 2)=ibaddr_lp11(12 downto 2) then
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ibsel := '1';
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n.ibsel := '1';
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end if;
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end if;
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-- ibus transactions
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-- ibus transactions
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if ibsel = '1' then
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if r.ibsel = '1' then
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case IB_MREQ.addr(1 downto 1) is
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case IB_MREQ.addr(1 downto 1) is
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when ibaddr_csr => -- CSR -- control status -------------
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when ibaddr_csr => -- CSR -- control status -------------
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idout(csr_ibf_err) := r.err;
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idout(csr_ibf_err) := r.err;
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idout(csr_ibf_done) := r.done;
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idout(csr_ibf_done) := r.done;
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end if;
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end if;
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N_REGS <= n;
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N_REGS <= n;
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IB_SRES.dout <= idout;
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IB_SRES.dout <= idout;
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IB_SRES.ack <= ibsel;
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IB_SRES.ack <= r.ibsel and ibreq;
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IB_SRES.busy <= '0';
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IB_SRES.busy <= '0';
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RRI_LAM <= ilam;
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RB_LAM <= ilam;
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EI_REQ <= r.intreq;
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EI_REQ <= r.intreq;
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end process proc_next;
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end process proc_next;
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