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-- $Id: ibdr_minisys.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: ibdr_minisys.vhd 335 2010-10-24 22:24:23Z mueller $
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--
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--
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- ibdr_rk11
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-- ibdr_rk11
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-- ib_sres_or_4
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-- ib_sres_or_4
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-- ib_intmap
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-- ib_intmap
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-10-17 333 12.1 M53 xc3s1000-4 128 469 16 265 s 7.8
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-- 2010-10-17 314 12.1 M53 xc3s1000-4 122 472 16 269 s 7.6
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2009-07-12 233 1.0.7 reorder ports, add CE_USEC; add RESET and CE_USEC
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-- 2009-07-12 233 1.0.7 reorder ports, add CE_USEC; add RESET and CE_USEC
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-- to _dl11
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-- to _dl11
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-- 2009-05-31 221 1.0.6 add RESET to kw11l;
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-- 2009-05-31 221 1.0.6 add RESET to kw11l;
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-- 2009-05-24 219 1.0.5 _rk11 uses now CE_MSEC
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-- 2009-05-24 219 1.0.5 _rk11 uses now CE_MSEC
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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CE_USEC : in slbit; -- usec pulse
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CE_MSEC : in slbit; -- msec pulse
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CE_MSEC : in slbit; -- msec pulse
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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BRESET : in slbit; -- ibus reset
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BRESET : in slbit; -- ibus reset
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RRI_LAM : out slv16_1; -- remote attention vector
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RB_LAM : out slv16_1; -- remote attention vector
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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IB_SRES : out ib_sres_type; -- ibus response
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EI_ACKM : in slbit; -- interrupt acknowledge (from master)
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EI_ACKM : in slbit; -- interrupt acknowledge (from master)
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EI_PRI : out slv3; -- interrupt priority (to cpu)
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EI_PRI : out slv3; -- interrupt priority (to cpu)
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EI_VECT : out slv9_2; -- interrupt vector (to cpu)
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EI_VECT : out slv9_2; -- interrupt vector (to cpu)
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| Line 94... |
Line 101... |
(8#060#,4), -- line 2 DL11-RX
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(8#060#,4), -- line 2 DL11-RX
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(8#064#,4), -- line 1 DL11-TX
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(8#064#,4), -- line 1 DL11-TX
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intmap_init -- line 0
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intmap_init -- line 0
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);
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);
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signal RRI_LAM_DL11 : slbit := '0';
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signal RB_LAM_DL11 : slbit := '0';
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signal RRI_LAM_RK11 : slbit := '0';
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signal RB_LAM_RK11 : slbit := '0';
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signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
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signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
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signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
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signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
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signal IB_SRES_DL11 : ib_sres_type := ib_sres_init;
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signal IB_SRES_DL11 : ib_sres_type := ib_sres_init;
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signal IB_SRES_RK11 : ib_sres_type := ib_sres_init;
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signal IB_SRES_RK11 : ib_sres_type := ib_sres_init;
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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RESET => RESET,
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RESET => RESET,
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BRESET => BRESET,
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BRESET => BRESET,
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RRI_LAM => RRI_LAM_DL11,
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RB_LAM => RB_LAM_DL11,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_DL11,
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IB_SRES => IB_SRES_DL11,
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EI_REQ_RX => EI_REQ_DL11RX,
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EI_REQ_RX => EI_REQ_DL11RX,
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EI_REQ_TX => EI_REQ_DL11TX,
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EI_REQ_TX => EI_REQ_DL11TX,
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EI_ACK_RX => EI_ACK_DL11RX,
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EI_ACK_RX => EI_ACK_DL11RX,
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| Line 158... |
Line 165... |
RK11 : ibdr_rk11
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RK11 : ibdr_rk11
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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BRESET => BRESET,
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BRESET => BRESET,
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RRI_LAM => RRI_LAM_RK11,
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RB_LAM => RB_LAM_RK11,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_RK11,
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IB_SRES => IB_SRES_RK11,
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EI_REQ => EI_REQ_RK11,
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EI_REQ => EI_REQ_RK11,
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EI_ACK => EI_ACK_RK11
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EI_ACK => EI_ACK_RK11
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);
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);
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EI_ACK_KW11L <= EI_ACK(4);
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EI_ACK_KW11L <= EI_ACK(4);
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EI_ACK_RK11 <= EI_ACK(3);
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EI_ACK_RK11 <= EI_ACK(3);
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EI_ACK_DL11RX <= EI_ACK(2);
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EI_ACK_DL11RX <= EI_ACK(2);
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EI_ACK_DL11TX <= EI_ACK(1);
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EI_ACK_DL11TX <= EI_ACK(1);
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RRI_LAM(1) <= RRI_LAM_DL11;
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RB_LAM(1) <= RB_LAM_DL11;
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RRI_LAM(2) <= '0'; -- for 2nd DL11
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RB_LAM(2) <= '0'; -- for 2nd DL11
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RRI_LAM(3) <= '0'; -- for DZ11
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RB_LAM(3) <= '0'; -- for DZ11
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RRI_LAM(4) <= RRI_LAM_RK11;
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RB_LAM(4) <= RB_LAM_RK11;
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RRI_LAM(15 downto 5) <= (others=>'0');
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RB_LAM(15 downto 5) <= (others=>'0');
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end syn;
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end syn;
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No newline at end of file
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No newline at end of file
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