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-- $Id: rbd_tester.vhd 369 2011-03-13 22:39:26Z mueller $
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-- $Id: rbd_tester.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Dependencies: memlib/fifo_1c_dram_raw
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-- Dependencies: memlib/fifo_1c_dram_raw
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--
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--
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-- Test bench: rlink/tb/tb_rlink (used as test target)
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-- Test bench: rlink/tb/tb_rlink (used as test target)
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 12.1; ghdl 0.29
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-- Tool versions: xst 12.1, 13.1; ghdl 0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-12-12 344 12.1 M53d xc3s1000-4 78 204 32 133 s 8.0
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-- 2010-12-12 344 12.1 M53d xc3s1000-4 78 204 32 133 s 8.0
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-- 2010-12-04 343 12.1 M53d xc3s1000-4 75 214 32 136 s 9.3
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-- 2010-12-04 343 12.1 M53d xc3s1000-4 75 214 32 136 s 9.3
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-19 427 1.0.4 now numeric_std clean
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-- 2010-12-31 352 1.0.3 simplify irb_ack logic
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-- 2010-12-31 352 1.0.3 simplify irb_ack logic
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-- 2010-12-29 351 1.0.2 default addr 111101xx->111100xx
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-- 2010-12-29 351 1.0.2 default addr 111101xx->111100xx
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-- 2010-12-12 344 1.0.1 send 0101.. on busy or err; fix init and busy logic
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-- 2010-12-12 344 1.0.1 send 0101.. on busy or err; fix init and busy logic
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-- 2010-12-04 343 1.0 Initial version
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-- 2010-12-04 343 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- 9:00 r: return cycle length of last access
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-- 9:00 r: return cycle length of last access
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.memlib.all;
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use work.rblib.all;
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use work.rblib.all;
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entity rbd_tester is -- rbus dev: rbus tester
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entity rbd_tester is -- rbus dev: rbus tester
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-- complete rrirp_aif interface
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-- complete rrirp_aif interface
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generic (
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generic (
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RB_ADDR : slv8 := conv_std_logic_vector(2#11110000#,8));
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RB_ADDR : slv8 := slv(to_unsigned(2#11110000#,8)));
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type; -- rbus: response
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RB_SRES : out rb_sres_type; -- rbus: response
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FULL => FIFO_FULL
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FULL => FIFO_FULL
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);
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);
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if CLK'event and CLK='1' then
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if rising_edge(CLK) then
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if RESET = '1' then
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if RESET = '1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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-- rbus transactions
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-- rbus transactions
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if r.rbsel = '1' then
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if r.rbsel = '1' then
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if irbena = '1' then -- if request active
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if irbena = '1' then -- if request active
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if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
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if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
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n.cntbusy := unsigned(r.cntbusy) - 1; -- decrement busy timer
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n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
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end if;
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end if;
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if r.cntcyc /= cntcyc_max then -- if cycle counter < max
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if r.cntcyc /= cntcyc_max then -- if cycle counter < max
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n.cntcyc := unsigned(r.cntcyc) + 1; -- increment cycle counter
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n.cntcyc := slv(unsigned(r.cntcyc) + 1); -- increment cycle counter
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end if;
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end if;
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end if;
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end if;
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irb_ack := irbena; -- ack all (some rejects later)
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irb_ack := irbena; -- ack all (some rejects later)
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