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-- $Id: rlinktblib.vhd 389 2011-07-07 21:59:00Z mueller $
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-- $Id: rlinktblib.vhd 444 2011-12-25 10:04:58Z mueller $
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--
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Package Name: rlinktblib
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-- Package Name: rlinktblib
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-- Description: rlink test environment components
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-- Description: rlink test environment components
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-12-23 444 3.1 new clock iface for tbcore_rlink; drop .._dcm
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-- 2010-12-29 351 3.0.1 add rbtba_aif;
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-- 2010-12-29 351 3.0.1 add rbtba_aif;
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-- 2010-12-24 347 3.0 rename rritblib->rlinktblib, CP_*->RL_*;
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-- 2010-12-24 347 3.0 rename rritblib->rlinktblib, CP_*->RL_*;
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-- many rri->rlink renames; drop rbus parts;
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-- many rri->rlink renames; drop rbus parts;
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-- 2010-11-13 338 2.5.2 add rritb_core_dcm
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-- 2010-11-13 338 2.5.2 add rritb_core_dcm
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-- 2010-06-26 309 2.5.1 add rritb_sres_or_mon
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-- 2010-06-26 309 2.5.1 add rritb_sres_or_mon
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RB_STAT : out slv3 -- rbus: status flags
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RB_STAT : out slv3 -- rbus: status flags
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);
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);
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end component;
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end component;
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component tbcore_rlink is -- core of vhpi_cext based test bench
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component tbcore_rlink is -- core of vhpi_cext based test bench
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generic (
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CLK_PERIOD : time := 20 ns; -- clock period
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CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock)
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SETUP_TIME : time := 5 ns; -- setup time
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C2OUT_TIME : time := 10 ns); -- clock to output time
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port (
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port (
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CLK : out slbit; -- main clock
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CLK : in slbit; -- control interface clock
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RX_DATA : out slv8; -- read data (data ext->tb)
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CLK_STOP : out slbit; -- clock stop trigger
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RX_VAL : out slbit; -- read data valid (data ext->tb)
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RX_HOLD : in slbit; -- read data hold (data ext->tb)
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TX_DATA : in slv8; -- write data (data tb->ext)
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TX_ENA : in slbit -- write data enable (data tb->ext)
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);
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end component;
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component tbcore_rlink_dcm is -- dcm aware core of vhpi_cext based tb
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generic (
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CLKOSC_PERIOD : time := 20 ns; -- clock osc period
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CLKOSC_OFFSET : time := 200 ns; -- clock osc offset (time to start clk)
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SETUP_TIME : time := 5 ns; -- setup time
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C2OUT_TIME : time := 10 ns); -- clock to output time
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port (
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CLKOSC : out slbit; -- clock osc
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CLKSYS : in slbit; -- DCM derived system clock
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RX_DATA : out slv8; -- read data (data ext->tb)
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RX_DATA : out slv8; -- read data (data ext->tb)
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RX_VAL : out slbit; -- read data valid (data ext->tb)
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RX_VAL : out slbit; -- read data valid (data ext->tb)
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RX_HOLD : in slbit; -- read data hold (data ext->tb)
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RX_HOLD : in slbit; -- read data hold (data ext->tb)
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TX_DATA : in slv8; -- write data (data tb->ext)
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TX_DATA : in slv8; -- write data (data tb->ext)
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TX_ENA : in slbit -- write data enable (data tb->ext)
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TX_ENA : in slbit -- write data enable (data tb->ext)
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