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-- $Id: tb_rlink.vhd 351 2010-12-30 21:50:54Z mueller $
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-- $Id: tb_rlink.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- To test: rlink_core (via tbd_rlink_direct)
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-- To test: rlink_core (via tbd_rlink_direct)
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-- rlink_base (via tbd_rlink_serport)
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-- rlink_base (via tbd_rlink_serport)
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-- rlink_serport (via tbd_rlink_serport)
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-- rlink_serport (via tbd_rlink_serport)
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-19 427 3.0.7 fix crc8_update_tbl usage; now numeric_std clean
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-- 2010-12-29 351 3.0.6 use new rbd_tester addr 111100xx (from 111101xx)
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-- 2010-12-29 351 3.0.6 use new rbd_tester addr 111100xx (from 111101xx)
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-- 2010-12-26 348 3.0.5 use simbus to export clkcycle (for tbd_..serport)
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-- 2010-12-26 348 3.0.5 use simbus to export clkcycle (for tbd_..serport)
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-- 2010-12-23 347 3.0.4 use rb_mon, rlink_mon directly; rename CP_*->RL_*
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-- 2010-12-23 347 3.0.4 use rb_mon, rlink_mon directly; rename CP_*->RL_*
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-- 2010-12-22 346 3.0.3 add .rlmon and .rbmon commands
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-- 2010-12-22 346 3.0.3 add .rlmon and .rbmon commands
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-- 2010-12-21 345 3.0.2 rename commands .[rt]x... to [rt]x...;
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-- 2010-12-21 345 3.0.2 rename commands .[rt]x... to [rt]x...;
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.genlib.all;
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use work.genlib.all;
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RB_SRES_err <= RB_SRES.err;
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RB_SRES_err <= RB_SRES.err;
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RB_SRES_dout <= RB_SRES.dout;
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RB_SRES_dout <= RB_SRES.dout;
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RBTEST : rbd_tester
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RBTEST : rbd_tester
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generic map (
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generic map (
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RB_ADDR => conv_std_logic_vector(2#11110000#,8))
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RB_ADDR => slv(to_unsigned(2#11110000#,8)))
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => '0',
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RESET => '0',
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES,
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RB_SRES => RB_SRES,
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procedure do_tx8 (data : inout slv8) is
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procedure do_tx8 (data : inout slv8) is
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begin
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begin
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txlist(ntxlist) := '0' & data;
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txlist(ntxlist) := '0' & data;
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ntxlist := ntxlist + 1;
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ntxlist := ntxlist + 1;
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crc8_update_tbl(txcrc, data);
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txcrc := crc8_update_tbl(txcrc, data);
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end procedure do_tx8;
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end procedure do_tx8;
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procedure do_tx16 (data : inout slv16) is
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procedure do_tx16 (data : inout slv16) is
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begin
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begin
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do_tx8(data( 7 downto 0));
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do_tx8(data( 7 downto 0));
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procedure do_rx8 (data : inout slv8) is
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procedure do_rx8 (data : inout slv8) is
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begin
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begin
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sv_rxlist(sv_nrxlist) := '0' & data;
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sv_rxlist(sv_nrxlist) := '0' & data;
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sv_nrxlist := sv_nrxlist + 1;
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sv_nrxlist := sv_nrxlist + 1;
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crc8_update_tbl(rxcrc, data);
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rxcrc := crc8_update_tbl(rxcrc, data);
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end procedure do_rx8;
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end procedure do_rx8;
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procedure do_rx16 (data : inout slv16) is
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procedure do_rx16 (data : inout slv16) is
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begin
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begin
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do_rx8(data( 7 downto 0));
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do_rx8(data( 7 downto 0));
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proc_moni: process
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proc_moni: process
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variable oline : line;
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variable oline : line;
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begin
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begin
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loop
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loop
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wait until CLK'event and CLK='1';
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wait until rising_edge(CLK);
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wait for c2out_time;
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wait for c2out_time;
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if RL_VAL = '1' then
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if RL_VAL = '1' then
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writetimestamp(oline, SB_CLKCYCLE, ": moni");
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writetimestamp(oline, SB_CLKCYCLE, ": moni");
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write(oline, RL_DO(8), right, 3);
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write(oline, RL_DO(8), right, 3);
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