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# $Id: tb_rlink_serport_stim.dat 351 2010-12-30 21:50:54Z mueller $
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# $Id: tb_rlink_sp1c_stim.dat 442 2011-12-23 10:03:28Z mueller $
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#
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#
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# Revision History:
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# Revision History:
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# Date Rev Version Comment
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# Date Rev Version Comment
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# 2011-12-22 442 1.1 remove RTS tests (now obsolete)
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# 2010-12-29 351 1.0.1 use new rbd_tester addr 111100xx (from 111101xx)
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# 2010-12-29 351 1.0.1 use new rbd_tester addr 111100xx (from 111101xx)
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# 2010-12-26 348 1.0 Initial version (Test 3 from tb_rlink_stim.dat)
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# 2010-12-26 348 1.0 Initial version (Test 3 from tb_rlink_stim.dat)
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#
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#
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#---------------------------------------
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#---------------------------------------
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# rbus address mapping
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# rbus address mapping
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Line 136... |
txca 01110000 11110001
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txca 01110000 11110001
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txeop
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txeop
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#
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#
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.iowt 10
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.iowt 10
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#
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#
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C -----------------------------------------------------------------------------
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C Test 4: Test RTS throttling via wreg/rreg
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C Note: RTS_N response is *not* selfchecking, look into log and check
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C for 'RTS_N' lines.
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C
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C init (11111110:0000000000001000) fena(0),fwth(0),fdly(0),rtsoff(1),rtson(0)
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C fifo := 1000000010000000
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C fifo := 1000000010000001
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C fifo := 1000000010000010
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C fifo := 1000000010000011
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C fifo := 1000000110000000
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C fifo := 1000000110000001
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C fifo := 1000000110000010
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C fifo := 1000000110000011
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C fifo -> 8 read (will produce escapes for dl and dh, thus slow down a bit)
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C
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C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc
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C wreg: tx: - cmd(00001,010) addr(0010) dl dh ccrc
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C wreg: ....
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C wreg: tx: - cmd(01000,010) addr(0010) dl dh ccrc
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C rreg: tx: - cmd(10001,000) addr(0010) ccrc
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C ....
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C rreg: tx: - cmd(11000,000) addr(0010) ccrc
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C tx: - eop
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C rx: sop - cmd(110) stat crc
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C rx: - cmd(010) stat crc
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C ...
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C rx: - cmd(010) stat crc
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C rx: - cmd(000) dl dh stat crc
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C ...
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C rx: - cmd(000) dl dh stat crc
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C rx: - eop
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C
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#
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rxsop
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rxcs 11110110 00000000
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rxcs 00001010 00000000
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rxcs 00010010 00000000
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rxcs 00011010 00000000
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rxcs 00100010 00000000
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rxcs 00101010 00000000
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rxcs 00110010 00000000
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rxcs 00111010 00000000
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rxcs 01000010 00000000
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rxcds 10001000 1000000010000000 00000000
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rxcds 10010000 1000000010000001 00000000
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rxcds 10011000 1000000010000010 00000000
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rxcds 10100000 1000000010000011 00000000
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rxcds 10101000 1000000110000000 00000000
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rxcds 10110000 1000000110000001 00000000
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rxcds 10111000 1000000110000010 00000000
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rxcds 11000000 1000000110000011 00000000
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rxeop
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#
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txsop
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txcad 11110110 11111110 0000000000001000
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txcad 00001010 11110010 1000000010000000
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txcad 00010010 11110010 1000000010000001
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txcad 00011010 11110010 1000000010000010
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txcad 00100010 11110010 1000000010000011
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txcad 00101010 11110010 1000000110000000
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txcad 00110010 11110010 1000000110000001
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txcad 00111010 11110010 1000000110000010
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txcad 01000010 11110010 1000000110000011
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txca 10001000 11110010
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txca 10010000 11110010
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txca 10011000 11110010
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txca 10100000 11110010
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txca 10101000 11110010
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txca 10110000 11110010
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txca 10111000 11110010
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txca 11000000 11110010
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txeop
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#
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.iowt 10
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#
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C -----------------------------------------------------------------------------
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C Test 5: Test RTS flush pulse
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C Note: RTS_N response is *not* selfchecking, look into log and check
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C for 'RTS_N' lines.
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C
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C 1a. setup width=1, delay=1
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C
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C init (11111110:0001001001111110) fena(1),fwth(1),fdly(1),rtsoff(7),rtson(6)
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C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop
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#
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rxsop
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rxcs 11110110 00000000
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rxeop
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txsop
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txcad 11110110 11111110 0001001001111110
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txeop
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.iowt 10
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.wait 50
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C
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C 1b. test with wreg sequence
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C data := 0000000000000001
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C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
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C rx: sop - cmd(010) stat crc - eop
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C
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#
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rxsop
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rxcs 00001010 00000000
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rxeop
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txsop
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txcad 00001010 11110001 0000000000000001
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txeop
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.iowt 10
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.wait 50
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C
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C 2a. setup width=3, delay=1
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C
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C init (11111110:0001011001111110) fena(1),fwth(3),fdly(1),rtsoff(7),rtson(6)
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C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop
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#
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rxsop
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rxcs 11110110 00000000
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rxeop
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txsop
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txcad 11110110 11111110 0001011001111110
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txeop
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.iowt 10
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.wait 50
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C
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C 2b. test with wreg sequence
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C data := 0000000000000001
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C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
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C rx: sop - cmd(010) stat crc - eop
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#
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rxsop
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rxcs 00001010 00000000
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rxeop
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txsop
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txcad 00001010 11110001 0000000000000001
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txeop
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.iowt 10
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.wait 50
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#
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C
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C 3a. setup width=7, delay=7
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C
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C init (11111110:0001111111111110) fena(1),fwth(7),fdly(7),rtsoff(7),rtson(6)
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C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop
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#
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rxsop
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rxcs 11110110 00000000
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rxeop
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txsop
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txcad 11110110 11111110 0001111111111110
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txeop
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.iowt 10
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.wait 50
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C
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C 3b. test with wreg sequence
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C data := 0000000000000001
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C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
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C rx: sop - cmd(010) stat crc - eop
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#
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rxsop
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rxcs 00001010 00000000
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rxeop
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txsop
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txcad 00001010 11110001 0000000000000001
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txeop
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.iowt 10
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.wait 50
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#
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#==============================================================================
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#==============================================================================
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#
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#
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C -----------------------------------------------------------------------------
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C -----------------------------------------------------------------------------
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C Run down and Finish
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C Run down and Finish
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.iowt 10
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.iowt 10
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