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-- $Id: tbcore_rlink.vhd 351 2010-12-30 21:50:54Z mueller $
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-- $Id: tbcore_rlink.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Dependencies: simlib/simclk
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-- Dependencies: simlib/simclk
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--
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--
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-- To test: generic, any rlink_cext based target
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-- To test: generic, any rlink_cext based target
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 11.4; ghdl 0.26
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-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-19 427 3.0.1 now numeric_std clean
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-- 2010-12-29 351 3.0 rename rritb_core->tbcore_rlink; use rbv3 naming
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-- 2010-12-29 351 3.0 rename rritb_core->tbcore_rlink; use rbv3 naming
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-- 2010-06-05 301 1.1.2 rename .rpmon -> .rbmon
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-- 2010-06-05 301 1.1.2 rename .rpmon -> .rbmon
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-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit;
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-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit;
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-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib;
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-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib;
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-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup
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-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup
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-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
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-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.simlib.all;
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use work.simlib.all;
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wait for CLK_OFFSET;
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wait for CLK_OFFSET;
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wait for 10*CLK_PERIOD;
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wait for 10*CLK_PERIOD;
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stim_loop: loop
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stim_loop: loop
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wait until CLK_L'event and CLK_L='1';
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wait until rising_edge(CLK_L);
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wait for CLK_PERIOD-SETUP_TIME;
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wait for CLK_PERIOD-SETUP_TIME;
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SB_ADDR <= (others=>'Z');
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SB_ADDR <= (others=>'Z');
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SB_DATA <= (others=>'Z');
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SB_DATA <= (others=>'Z');
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icycle := conv_integer(unsigned(SB_CLKCYCLE));
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icycle := to_integer(unsigned(SB_CLKCYCLE));
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RX_VAL <= '0';
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RX_VAL <= '0';
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if RX_HOLD = '0' then
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if RX_HOLD = '0' then
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irxint := rlink_cext_getbyte(icycle);
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irxint := rlink_cext_getbyte(icycle);
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if irxint >= 0 then
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if irxint >= 0 then
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if irxint <= 16#ff# then -- normal data byte
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if irxint <= 16#ff# then -- normal data byte
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RX_DATA <= conv_std_logic_vector(irxint, 8);
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RX_DATA <= slv(to_unsigned(irxint, 8));
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RX_VAL <= '1';
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RX_VAL <= '1';
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elsif irxint >= 16#1000000# then -- out-of-band message
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elsif irxint >= 16#1000000# then -- out-of-band message
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irxslv := conv_std_logic_vector(irxint, 24);
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irxslv := slv(to_unsigned(irxint mod 16#1000000#, 24));
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iaddr := irxslv(23 downto 16);
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iaddr := irxslv(23 downto 16);
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idata := irxslv(15 downto 0);
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idata := irxslv(15 downto 0);
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writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG");
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writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG");
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write(oline, irxslv(23 downto 16), right, 9);
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write(oline, irxslv(23 downto 16), right, 9);
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write(oline, irxslv(15 downto 8), right, 9);
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write(oline, irxslv(15 downto 8), right, 9);
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write(oline, string'(" : "));
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write(oline, string'(" : "));
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writeoct(oline, iaddr, right, 3);
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writeoct(oline, iaddr, right, 3);
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writeoct(oline, idata, right, 7);
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writeoct(oline, idata, right, 7);
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writeline(output, oline);
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writeline(output, oline);
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if unsigned(iaddr) = 0 then
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if unsigned(iaddr) = 0 then
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ibit := conv_integer(unsigned(idata(15 downto 8)));
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ibit := to_integer(unsigned(idata(15 downto 8)));
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r_sb_cntl(ibit) := idata(0);
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r_sb_cntl(ibit) := idata(0);
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else
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else
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SB_ADDR <= iaddr;
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SB_ADDR <= iaddr;
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SB_DATA <= idata;
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SB_DATA <= idata;
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SB_VAL <= '1';
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SB_VAL <= '1';
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variable itxrc : integer := 0;
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variable itxrc : integer := 0;
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variable oline : line;
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variable oline : line;
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begin
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begin
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loop
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loop
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wait until CLK_L'event and CLK_L='1';
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wait until rising_edge(CLK_L);
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wait for C2OUT_TIME;
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wait for C2OUT_TIME;
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if TX_ENA = '1' then
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if TX_ENA = '1' then
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itxdata := conv_integer(unsigned(TX_DATA));
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itxdata := to_integer(unsigned(TX_DATA));
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itxrc := rlink_cext_putbyte(itxdata);
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itxrc := rlink_cext_putbyte(itxdata);
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assert itxrc=0
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assert itxrc=0
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report "rlink_cext_putbyte error: " & integer'image(itxrc)
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report "rlink_cext_putbyte error: " & integer'image(itxrc)
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severity failure;
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severity failure;
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end if;
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end if;
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