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-- $Id: tbcore_rlink.vhd 445 2011-12-26 21:19:26Z mueller $
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-- $Id: tbcore_rlink.vhd 469 2013-01-05 12:29:44Z mueller $
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--
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--
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
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-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2013-01-04 469 3.1.2 use 1ns wait for .sinit to allow simbus debugging
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-- 2011-12-25 445 3.1.1 add SB_ init drivers to avoid SB_VAL='U' at start
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-- 2011-12-25 445 3.1.1 add SB_ init drivers to avoid SB_VAL='U' at start
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-- 2011-12-23 444 3.1 redo clock handling, remove simclk, CLK now input
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-- 2011-12-23 444 3.1 redo clock handling, remove simclk, CLK now input
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-- 2011-11-19 427 3.0.1 now numeric_std clean
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-- 2011-11-19 427 3.0.1 now numeric_std clean
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-- 2010-12-29 351 3.0 rename rritb_core->tbcore_rlink; use rbv3 naming
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-- 2010-12-29 351 3.0 rename rritb_core->tbcore_rlink; use rbv3 naming
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-- 2010-06-05 301 1.1.2 rename .rpmon -> .rbmon
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-- 2010-06-05 301 1.1.2 rename .rpmon -> .rbmon
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readgen_ea(iline, iaddr, 8);
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readgen_ea(iline, iaddr, 8);
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readgen_ea(iline, idata, 8);
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readgen_ea(iline, idata, 8);
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SB_ADDR <= iaddr;
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SB_ADDR <= iaddr;
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SB_DATA <= idata;
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SB_DATA <= idata;
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SB_VAL <= 'H';
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SB_VAL <= 'H';
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wait for 0 ns;
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wait for 1 ns;
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SB_VAL <= 'L';
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SB_VAL <= 'L';
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SB_ADDR <= (others=>'L');
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SB_ADDR <= (others=>'L');
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SB_DATA <= (others=>'L');
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SB_DATA <= (others=>'L');
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wait for 0 ns;
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wait for 1 ns;
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when others => -- bad command
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when others => -- bad command
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write(oline, string'("?? unknown command: "));
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write(oline, string'("?? unknown command: "));
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write(oline, dname);
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write(oline, dname);
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writeline(output, oline);
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writeline(output, oline);
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