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-- $Id: rritb_core.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: tbcore_rlink.vhd 351 2010-12-30 21:50:54Z mueller $
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--
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: rritb_core - sim
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-- Module Name: tbcore_rlink - sim
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-- Description: Core for a rri and cext based test bench
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-- Description: Core for a rlink_cext based test bench
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--
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--
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-- Dependencies: simlib/simclk
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-- Dependencies: simlib/simclk
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--
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--
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-- To test: generic, any rri/cext based target
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-- To test: generic, any rlink_cext based target
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 11.4; ghdl 0.26
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-- Tool versions: xst 11.4; ghdl 0.26
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-06-05 301 1.1.2 renamed .rpmon -> .rbmon
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-- 2010-12-29 351 3.0 rename rritb_core->tbcore_rlink; use rbv3 naming
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-- 2010-06-05 301 1.1.2 rename .rpmon -> .rbmon
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-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit;
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-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit;
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-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib;
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-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib;
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-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup
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-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup
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-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
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-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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use std.textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.simlib.all;
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use work.simlib.all;
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use work.simbus.all;
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use work.simbus.all;
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use work.rritblib.all;
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use work.rblib.all;
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use work.vhpi_rriext.all;
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use work.rlinklib.all;
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use work.rlinktblib.all;
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use work.rlink_cext_vhpi.all;
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entity rritb_core is -- core of rri/cext based test bench
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entity tbcore_rlink is -- core of rlink_cext based test bench
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generic (
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generic (
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CLK_PERIOD : time := 20 ns; -- clock period
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CLK_PERIOD : time := 20 ns; -- clock period
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CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock)
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CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock)
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SETUP_TIME : time := 5 ns; -- setup time
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SETUP_TIME : time := 5 ns; -- setup time
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C2OUT_TIME : time := 10 ns); -- clock to output time
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C2OUT_TIME : time := 10 ns); -- clock to output time
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RX_VAL : out slbit; -- read data valid (data ext->tb)
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RX_VAL : out slbit; -- read data valid (data ext->tb)
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RX_HOLD : in slbit; -- read data hold (data ext->tb)
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RX_HOLD : in slbit; -- read data hold (data ext->tb)
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TX_DATA : in slv8; -- write data (data tb->ext)
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TX_DATA : in slv8; -- write data (data tb->ext)
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TX_ENA : in slbit -- write data enable (data tb->ext)
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TX_ENA : in slbit -- write data enable (data tb->ext)
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);
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);
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end rritb_core;
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end tbcore_rlink;
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architecture sim of rritb_core is
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architecture sim of tbcore_rlink is
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signal CLK_L : slbit := '0';
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signal CLK_L : slbit := '0';
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signal CLK_STOP : slbit := '0';
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signal CLK_STOP : slbit := '0';
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begin
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begin
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);
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);
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CLK <= CLK_L;
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CLK <= CLK_L;
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proc_conf: process
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proc_conf: process
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file fconf : text open read_mode is "tb_rriext_conf";
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file fconf : text open read_mode is "rlink_cext_conf";
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variable iline : line;
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variable iline : line;
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variable oline : line;
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variable oline : line;
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variable ok : boolean;
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variable ok : boolean;
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variable dname : string(1 to 6) := (others=>' ');
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variable dname : string(1 to 6) := (others=>' ');
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variable ien : slbit := '0';
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variable ien : slbit := '0';
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SB_CNTL(ibit) <= 'H';
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SB_CNTL(ibit) <= 'H';
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else
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else
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SB_CNTL(ibit) <= 'L';
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SB_CNTL(ibit) <= 'L';
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end if;
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end if;
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when ".cpmon" => -- .cpmon
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when ".rlmon" => -- .rlmon
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read_ea(iline, ien);
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read_ea(iline, ien);
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if ien = '1' then
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if ien = '1' then
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SB_CNTL(sbcntl_sbf_cpmon) <= 'H';
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SB_CNTL(sbcntl_sbf_rlmon) <= 'H';
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else
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else
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SB_CNTL(sbcntl_sbf_cpmon) <= 'L';
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SB_CNTL(sbcntl_sbf_rlmon) <= 'L';
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end if;
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end if;
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when ".rbmon" => -- .rbmon
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when ".rbmon" => -- .rbmon
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read_ea(iline, ien);
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read_ea(iline, ien);
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if ien = '1' then
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if ien = '1' then
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icycle := conv_integer(unsigned(SB_CLKCYCLE));
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icycle := conv_integer(unsigned(SB_CLKCYCLE));
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RX_VAL <= '0';
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RX_VAL <= '0';
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if RX_HOLD = '0' then
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if RX_HOLD = '0' then
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irxint := cext_getbyte(icycle);
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irxint := rlink_cext_getbyte(icycle);
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if irxint >= 0 then
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if irxint >= 0 then
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if irxint <= 16#ff# then -- normal data byte
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if irxint <= 16#ff# then -- normal data byte
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RX_DATA <= conv_std_logic_vector(irxint, 8);
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RX_DATA <= conv_std_logic_vector(irxint, 8);
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RX_VAL <= '1';
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RX_VAL <= '1';
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elsif irxint >= 16#1000000# then -- out-of-band message
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elsif irxint >= 16#1000000# then -- out-of-band message
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end if;
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end if;
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end if;
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end if;
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elsif irxint = -1 then -- end-of-file seen
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elsif irxint = -1 then -- end-of-file seen
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exit stim_loop;
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exit stim_loop;
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else
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else
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report "cext_getbyte error: " & integer'image(-irxint)
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report "rlink_cext_getbyte error: " & integer'image(-irxint)
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severity failure;
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severity failure;
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end if;
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end if;
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end if;
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end if;
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SB_CNTL <= r_sb_cntl;
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SB_CNTL <= r_sb_cntl;
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loop
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loop
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wait until CLK_L'event and CLK_L='1';
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wait until CLK_L'event and CLK_L='1';
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wait for C2OUT_TIME;
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wait for C2OUT_TIME;
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if TX_ENA = '1' then
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if TX_ENA = '1' then
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itxdata := conv_integer(unsigned(TX_DATA));
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itxdata := conv_integer(unsigned(TX_DATA));
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itxrc := cext_putbyte(itxdata);
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itxrc := rlink_cext_putbyte(itxdata);
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assert itxrc=0
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assert itxrc=0
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report "cext_putbyte error: " & integer'image(itxrc)
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report "rlink_cext_putbyte error: " & integer'image(itxrc)
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severity failure;
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severity failure;
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end if;
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end if;
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end loop;
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end loop;
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