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-- $Id: pdp11_bram.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: pdp11_bram.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Description: pdp11: BRAM based ext. memory dummy
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-- Description: pdp11: BRAM based ext. memory dummy
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--
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--
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-- Dependencies: memlib/ram_2swsr_rfirst_gen
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-- Dependencies: memlib/ram_2swsr_rfirst_gen
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.0.3 now numeric_std clean
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-- 2008-03-01 120 1.0.2 add addrzero constant to avoid XST errors
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-- 2008-03-01 120 1.0.2 add addrzero constant to avoid XST errors
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-- 2008-02-23 118 1.0.1 AWIDTH now a generic port
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-- 2008-02-23 118 1.0.1 AWIDTH now a generic port
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-- 2008-02-17 117 1.0 Initial version
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-- 2008-02-17 117 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.memlib.all;
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use work.pdp11.all;
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use work.pdp11.all;
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);
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);
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if CLK'event and CLK='1' then
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if rising_edge(CLK) then
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if GRESET = '1' then
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if GRESET = '1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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