| Line 1... |
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-- $Id: pdp11_core_rri.vhd 335 2010-10-24 22:24:23Z mueller $
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-- $Id: pdp11_core_rbus.vhd 352 2011-01-02 13:01:37Z mueller $
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--
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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| Line 10... |
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: pdp11_core_rri - syn
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-- Module Name: pdp11_core_rbus - syn
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-- Description: pdp11: core to rri register port interface
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-- Description: pdp11: core to rbus interface
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: tb/tb_rritba_pdp11core
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-- Test bench: tb/tb_rlink_tba_pdp11core
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-- tb/tb_rripdp_pdp11core
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-- tb/tb_rriext_pdp11core
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.26
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.26
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-- Revision History: -
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-- Revision History: -
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-12-29 351 1.1 renamed from pdp11_core_rri; ported to rbv3
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-- 2010-10-23 335 1.2.3 rename RRI_LAM->RB_LAM;
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-- 2010-10-23 335 1.2.3 rename RRI_LAM->RB_LAM;
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-- 2010-06-20 308 1.2.2 use c_ibrb_ibf_ def's
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-- 2010-06-20 308 1.2.2 use c_ibrb_ibf_ def's
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-- 2010-06-18 306 1.2.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
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-- 2010-06-18 306 1.2.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
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-- add ibrb register and ibr window logic
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-- add ibrb register and ibr window logic
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-- 2010-06-13 305 1.2 add CP_ADDR in port; mostly rewritten for new
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-- 2010-06-13 305 1.2 add CP_ADDR in port; mostly rewritten for new
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| Line 80... |
Line 79... |
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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|
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.rrilib.all;
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use work.rblib.all;
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use work.pdp11.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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|
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entity pdp11_core_rri is -- core to rri reg port interface
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entity pdp11_core_rbus is -- core to rbus interface
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generic (
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generic (
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RB_ADDR_CORE : slv8 := conv_std_logic_vector(2#00000000#,8);
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RB_ADDR_CORE : slv8 := conv_std_logic_vector(2#00000000#,8);
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RB_ADDR_IBUS : slv8 := conv_std_logic_vector(2#10000000#,8));
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RB_ADDR_IBUS : slv8 := conv_std_logic_vector(2#10000000#,8));
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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| Line 103... |
Line 102... |
CP_ADDR : out cp_addr_type; -- console address port
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CP_ADDR : out cp_addr_type; -- console address port
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CP_DIN : out slv16; -- console data in
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CP_DIN : out slv16; -- console data in
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CP_STAT : in cp_stat_type; -- console status port
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CP_STAT : in cp_stat_type; -- console status port
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CP_DOUT : in slv16 -- console data out
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CP_DOUT : in slv16 -- console data out
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);
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);
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end pdp11_core_rri;
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end pdp11_core_rbus;
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architecture syn of pdp11_core_rri is
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architecture syn of pdp11_core_rbus is
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|
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type state_type is (
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type state_type is (
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s_idle, -- s_idle: wait for rp access
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s_idle, -- s_idle: wait for rp access
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s_cpwait, -- s_cpwait: wait for cp port ack
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s_cpwait, -- s_cpwait: wait for cp port ack
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s_cpstep -- s_cpstep: wait for cpustep done
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s_cpstep -- s_cpstep: wait for cpustep done
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);
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);
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|
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type regs_type is record
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type regs_type is record
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state : state_type; -- state
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state : state_type; -- state
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rbselc : slbit; -- rbus select for core
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rbseli : slbit; -- rbus select for ibus
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cpreq : slbit; -- cp request flag
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cpreq : slbit; -- cp request flag
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cpfunc : slv5; -- cp function
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cpfunc : slv5; -- cp function
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cpugo_1 : slbit; -- prev cycle cpugo
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cpugo_1 : slbit; -- prev cycle cpugo
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addr : slv22_1; -- address register
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addr : slv22_1; -- address register
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ena_22bit : slbit; -- 22bit enable
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ena_22bit : slbit; -- 22bit enable
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| Line 131... |
Line 132... |
waitstep : slbit; -- at cmdack: wait for cpu step complete
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waitstep : slbit; -- at cmdack: wait for cpu step complete
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end record regs_type;
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end record regs_type;
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|
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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s_idle, -- state
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s_idle, -- state
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'0','0', -- rbselc,rbseli
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'0', -- cpreq
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'0', -- cpreq
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(others=>'0'), -- cpfunc
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(others=>'0'), -- cpfunc
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'0', -- cpugo_1
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'0', -- cpugo_1
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(others=>'0'), -- addr
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(others=>'0'), -- addr
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'0','0', -- ena_22bit, ena_ubmap
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'0','0', -- ena_22bit, ena_ubmap
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| Line 163... |
Line 165... |
proc_next: process (R_REGS, RB_MREQ, CP_STAT, CP_DOUT)
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proc_next: process (R_REGS, RB_MREQ, CP_STAT, CP_DOUT)
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|
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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|
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variable irb_selc : slbit := '0';
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variable irb_seli : slbit := '0';
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variable irb_ack : slbit := '0';
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variable irb_ack : slbit := '0';
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variable irb_busy : slbit := '0';
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variable irb_busy : slbit := '0';
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variable irb_err : slbit := '0';
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variable irb_err : slbit := '0';
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variable irb_dout : slv16 := (others=>'0');
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variable irb_dout : slv16 := (others=>'0');
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variable irb_lam : slbit := '0';
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variable irb_lam : slbit := '0';
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variable irbena : slbit := '0';
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|
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variable icpreq : slbit := '0';
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variable icpreq : slbit := '0';
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variable icpureset : slbit := '0';
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variable icpureset : slbit := '0';
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variable icpaddr : cp_addr_type := cp_addr_init;
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variable icpaddr : cp_addr_type := cp_addr_init;
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|
|
begin
|
begin
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|
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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|
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irb_selc := '0';
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irb_seli := '0';
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irb_ack := '0';
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irb_ack := '0';
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irb_busy := '0';
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irb_busy := '0';
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irb_err := '0';
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irb_err := '0';
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irb_dout := (others=>'0');
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irb_dout := (others=>'0');
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irb_lam := '0';
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irb_lam := '0';
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|
|
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irbena := RB_MREQ.re or RB_MREQ.we;
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|
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icpreq := '0';
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icpreq := '0';
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icpureset := '0';
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icpureset := '0';
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|
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if RB_MREQ.req='1' then
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-- look for init's against the rbus base address, generate subsystem resets
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if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR_CORE then
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icpureset := RB_MREQ.din(0);
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|
end if;
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-- rbus address decoder
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n.rbseli := '0';
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n.rbselc := '0';
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if RB_MREQ.aval='1' then
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if RB_MREQ.addr(7 downto 5)=RB_ADDR_CORE(7 downto 5) then
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if RB_MREQ.addr(7 downto 5)=RB_ADDR_CORE(7 downto 5) then
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irb_selc := '1';
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n.rbselc := '1';
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irb_ack := '1'; -- ack all, unless reject or busy
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end if;
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end if;
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if RB_MREQ.addr(7 downto 5)=RB_ADDR_IBUS(7 downto 5) then
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if RB_MREQ.addr(7 downto 5)=RB_ADDR_IBUS(7 downto 5) then
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irb_seli := '1';
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n.rbseli := '1';
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irb_ack := '1'; -- ack all, unless reject or busy
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end if;
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end if;
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end if;
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end if;
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-- look for init's against the rbus base address, generate subsystem resets
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if (r.rbselc='1' or r.rbseli='1') and irbena='1' then
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if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR_CORE then
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irb_ack := '1'; -- ack all (maybe rejected later)
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icpureset := RB_MREQ.din(0);
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end if;
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end if;
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case r.state is
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case r.state is
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when s_idle => -- s_idle: wait for rbus access ------
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when s_idle => -- s_idle: wait for rbus access ------
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n.doinc := '0';
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n.doinc := '0';
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n.waitstep := '0';
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n.waitstep := '0';
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|
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if irb_seli = '1' then
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if r.rbseli = '1' then
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if irbena = '1' then
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n.cpfunc := c_cpfunc_rmem;
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n.cpfunc := c_cpfunc_rmem;
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n.cpfunc(0) := RB_MREQ.we;
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n.cpfunc(0) := RB_MREQ.we;
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icpreq := '1';
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icpreq := '1';
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end if;
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elsif irb_selc = '1' then
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elsif r.rbselc = '1' then
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|
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case RB_MREQ.addr(4 downto 0) is
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case RB_MREQ.addr(4 downto 0) is
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|
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when c_rbaddr_conf => -- conf -------------------------
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when c_rbaddr_conf => -- conf -------------------------
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null; -- currently no action
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null; -- currently no action
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|
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when c_rbaddr_cntl => -- cntl -------------------------
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when c_rbaddr_cntl => -- cntl -------------------------
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if irbena = '1' then
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n.cpfunc := RB_MREQ.din(n.cpfunc'range);
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n.cpfunc := RB_MREQ.din(n.cpfunc'range);
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end if;
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if RB_MREQ.we = '1' then
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if RB_MREQ.we = '1' then
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icpreq := '1';
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icpreq := '1';
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if RB_MREQ.din(3 downto 0) = c_cpfunc_step(3 downto 0) then
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if RB_MREQ.din(3 downto 0) = c_cpfunc_step(3 downto 0) then
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n.waitstep := '1';
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n.waitstep := '1';
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end if;
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end if;
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| Line 243... |
Line 253... |
irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo;
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irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo;
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irb_dout(c_stat_rbf_cpuhalt) := CP_STAT.cpuhalt;
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irb_dout(c_stat_rbf_cpuhalt) := CP_STAT.cpuhalt;
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irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust;
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irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust;
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|
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when c_rbaddr_psw => -- psw --------------------------
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when c_rbaddr_psw => -- psw --------------------------
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|
if irbena = '1' then
|
n.cpfunc := c_cpfunc_rpsw;
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n.cpfunc := c_cpfunc_rpsw;
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n.cpfunc(0) := RB_MREQ.we;
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n.cpfunc(0) := RB_MREQ.we;
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icpreq := '1';
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icpreq := '1';
|
|
end if;
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|
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when c_rbaddr_al => -- al ---------------------------
|
when c_rbaddr_al => -- al ---------------------------
|
irb_dout(c_al_rbf_addr) := r.addr(c_al_rbf_addr);
|
irb_dout(c_al_rbf_addr) := r.addr(c_al_rbf_addr);
|
if RB_MREQ.we = '1' then
|
if RB_MREQ.we = '1' then
|
n.addr := (others=>'0'); -- write to al clears ah !!
|
n.addr := (others=>'0'); -- write to al clears ah !!
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| Line 267... |
Line 279... |
n.ena_22bit := RB_MREQ.din(c_ah_rbf_ena_22bit);
|
n.ena_22bit := RB_MREQ.din(c_ah_rbf_ena_22bit);
|
n.ena_ubmap := RB_MREQ.din(c_ah_rbf_ena_ubmap);
|
n.ena_ubmap := RB_MREQ.din(c_ah_rbf_ena_ubmap);
|
end if;
|
end if;
|
|
|
when c_rbaddr_mem => -- mem -----------------
|
when c_rbaddr_mem => -- mem -----------------
|
|
if irbena = '1' then
|
n.cpfunc := c_cpfunc_rmem;
|
n.cpfunc := c_cpfunc_rmem;
|
n.cpfunc(0) := RB_MREQ.we;
|
n.cpfunc(0) := RB_MREQ.we;
|
icpreq := '1';
|
icpreq := '1';
|
|
end if;
|
|
|
when c_rbaddr_memi => -- memi ----------------
|
when c_rbaddr_memi => -- memi ----------------
|
|
if irbena = '1' then
|
n.cpfunc := c_cpfunc_rmem;
|
n.cpfunc := c_cpfunc_rmem;
|
n.cpfunc(0) := RB_MREQ.we;
|
n.cpfunc(0) := RB_MREQ.we;
|
n.doinc := '1';
|
n.doinc := '1';
|
icpreq := '1';
|
icpreq := '1';
|
|
end if;
|
|
|
when c_rbaddr_r0 | c_rbaddr_r1 |
|
when c_rbaddr_r0 | c_rbaddr_r1 |
|
c_rbaddr_r2 | c_rbaddr_r3 |
|
c_rbaddr_r2 | c_rbaddr_r3 |
|
c_rbaddr_r4 | c_rbaddr_r5 |
|
c_rbaddr_r4 | c_rbaddr_r5 |
|
c_rbaddr_sp | c_rbaddr_pc => -- r* ------------------
|
c_rbaddr_sp | c_rbaddr_pc => -- r* ------------------
|
|
if irbena = '1' then
|
n.cpfunc := c_cpfunc_rreg;
|
n.cpfunc := c_cpfunc_rreg;
|
n.cpfunc(0) := RB_MREQ.we;
|
n.cpfunc(0) := RB_MREQ.we;
|
icpreq := '1';
|
icpreq := '1';
|
|
end if;
|
|
|
when c_rbaddr_ibrb => -- ibrb ----------------
|
when c_rbaddr_ibrb => -- ibrb ----------------
|
irb_dout(c_ibrb_ibf_base) := r.ibrbase;
|
irb_dout(c_ibrb_ibf_base) := r.ibrbase;
|
irb_dout(c_ibrb_ibf_be) := r.ibrberet;
|
irb_dout(c_ibrb_ibf_be) := r.ibrberet;
|
if RB_MREQ.we = '1' then
|
if RB_MREQ.we = '1' then
|
| Line 314... |
Line 332... |
end if;
|
end if;
|
|
|
when s_cpwait => -- s_cpwait: wait for cp port ack ----
|
when s_cpwait => -- s_cpwait: wait for cp port ack ----
|
n.cpreq := '0'; -- cpreq only for 1 cycle
|
n.cpreq := '0'; -- cpreq only for 1 cycle
|
|
|
if (irb_selc or irb_seli) = '0' then -- rbus cycle abort
|
if (r.rbselc or r.rbseli)='0' or irbena='0' then -- rbus cycle abort
|
n.state := s_idle; -- quit
|
n.state := s_idle; -- quit
|
else
|
else
|
irb_dout := CP_DOUT;
|
irb_dout := CP_DOUT;
|
irb_err := CP_STAT.cmderr or CP_STAT.cmdmerr;
|
irb_err := CP_STAT.cmderr or CP_STAT.cmdmerr;
|
if CP_STAT.cmdack = '1' then -- normal cycle end
|
if CP_STAT.cmdack = '1' then -- normal cycle end
|
| Line 335... |
Line 353... |
irb_busy := '1';
|
irb_busy := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when s_cpstep => -- s_cpstep: wait for cpustep done ---
|
when s_cpstep => -- s_cpstep: wait for cpustep done ---
|
if irb_selc = '0' then -- rbus cycle abort
|
if r.rbselc='0' or irbena='0' then -- rbus cycle abort
|
n.state := s_idle; -- quit
|
n.state := s_idle; -- quit
|
else
|
else
|
if CP_STAT.cpustep = '0' then -- cpustep done
|
if CP_STAT.cpustep = '0' then -- cpustep done
|
n.state := s_idle;
|
n.state := s_idle;
|
else
|
else
|
| Line 355... |
Line 373... |
icpaddr.racc := '0';
|
icpaddr.racc := '0';
|
icpaddr.be := "11";
|
icpaddr.be := "11";
|
icpaddr.ena_22bit := r.ena_22bit;
|
icpaddr.ena_22bit := r.ena_22bit;
|
icpaddr.ena_ubmap := r.ena_ubmap;
|
icpaddr.ena_ubmap := r.ena_ubmap;
|
|
|
if irb_seli = '1' then
|
if r.rbseli = '1' and irbena = '1' then
|
icpaddr.addr(15 downto 13) := "111";
|
icpaddr.addr(15 downto 13) := "111";
|
icpaddr.addr(c_ibrb_ibf_base) := r.ibrbase;
|
icpaddr.addr(c_ibrb_ibf_base) := r.ibrbase;
|
icpaddr.addr(5 downto 1) := RB_MREQ.addr(4 downto 0);
|
icpaddr.addr(5 downto 1) := RB_MREQ.addr(4 downto 0);
|
icpaddr.racc := '1';
|
icpaddr.racc := '1';
|
icpaddr.be := r.ibrbe;
|
icpaddr.be := r.ibrbe;
|
