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-- $Id: pdp11_tmu.vhd 333 2010-10-17 21:18:33Z mueller $
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-- $Id: pdp11_tmu.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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--
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--
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: ghdl 0.18-0.25
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-- Tool versions: ghdl 0.18-0.29
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.0.7 now numeric_std clean
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-- 2010-10-17 333 1.0.6 use ibus V2 interface
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-- 2010-10-17 333 1.0.6 use ibus V2 interface
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-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
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-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
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-- 2009-05-10 214 1.0.4 add ENA signal (trace enable)
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-- 2009-05-10 214 1.0.4 add ENA signal (trace enable)
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-- 2008-12-14 177 1.0.3 write gpr_* of DM_STAT_DP and dp_ireg_we_last
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-- 2008-12-14 177 1.0.3 write gpr_* of DM_STAT_DP and dp_ireg_we_last
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-- 2008-12-13 176 1.0.2 write only cycle currently used by tmu_conf
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-- 2008-12-13 176 1.0.2 write only cycle currently used by tmu_conf
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-- 2008-04-19 137 1.0 Initial version
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-- 2008-04-19 137 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.simlib.all;
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use work.simlib.all;
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variable wcycle : boolean := false;
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variable wcycle : boolean := false;
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file ofile : text open write_mode is "tmu_ofile";
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file ofile : text open write_mode is "tmu_ofile";
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begin
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begin
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if CLK'event and CLK='1' then
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if rising_edge(CLK) then
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if R_FIRST = '1' then
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if R_FIRST = '1' then
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R_FIRST <= '0';
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R_FIRST <= '0';
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write(oline, string'("#"));
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write(oline, string'("#"));
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write(oline, string'(" clkcycle:d"));
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write(oline, string'(" clkcycle:d"));
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if ENA = '0' then -- if not enabled
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if ENA = '0' then -- if not enabled
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wcycle := false; -- force to not logged...
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wcycle := false; -- force to not logged...
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end if;
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end if;
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if wcycle then
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if wcycle then
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write(oline, conv_integer(unsigned(SB_CLKCYCLE)), right, 9);
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write(oline, to_integer(unsigned(SB_CLKCYCLE)), right, 9);
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write(oline, string'(" 0"));
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write(oline, string'(" 0"));
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writeoct(oline, DM_STAT_DP.pc, right, 7);
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writeoct(oline, DM_STAT_DP.pc, right, 7);
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writeoct(oline, ipsw, right, 7);
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writeoct(oline, ipsw, right, 7);
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writeoct(oline, DM_STAT_DP.ireg, right, 7);
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writeoct(oline, DM_STAT_DP.ireg, right, 7);
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write(oline, DM_STAT_DP.ireg_we, right, 2);
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write(oline, DM_STAT_DP.ireg_we, right, 2);
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