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-- $Id: tb_pdp11_core.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: tb_pdp11core.vhd 352 2011-01-02 13:01:37Z mueller $
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--
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--
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-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: tb_pdp11_core - sim
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-- Module Name: tb_pdp11core - sim
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-- Description: Test bench for pdp11_core
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-- Description: Test bench for pdp11_core
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--
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--
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-- Dependencies: simlib/simclk
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-- Dependencies: simlib/simclk
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-- tbd_pdp11_core [UUT]
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-- tbd_pdp11core [UUT]
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-- pdp11_intmap
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-- pdp11_intmap
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--
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--
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-- To test: pdp11_core
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-- To test: pdp11_core
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: ghdl 0.18-0.29; ISim 11.3
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-- Tool versions: ghdl 0.18-0.29; ISim 11.3
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--
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--
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-- Verified (with tb_pdp11_core_stim.dat):
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-- Verified (with tb_pdp11core_stim.dat):
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-- Date Rev Code ghdl ise Target Comment
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-- Date Rev Code ghdl ise Target Comment
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-- 2010-12-30 351 - 0.29 - - u:ok
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-- 2010-12-30 351 _ssim 0.29 12.1 M53d xc3s1000 u:ok
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-- 2010-06-20 308 - 0.29 - - u:ok
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-- 2010-06-20 308 - 0.29 - - u:ok
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-- 2009-11-22 252 - 0.26 - - u:ok
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-- 2009-11-22 252 - 0.26 - - u:ok
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-- 2007-12-30 107 - 0.25 - - u:ok
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-- 2007-12-30 107 - 0.25 - - u:ok
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-- 2007-10-26 92 _tsim 0.26 8.1.03 I27 xc3s1000 c:fail -> blog_ghdl
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-- 2007-10-26 92 _tsim 0.26 8.1.03 I27 xc3s1000 c:fail -> blog_ghdl
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-- 2007-10-26 92 _tsim 0.26 9.2.02 J39 xc3s1000 d:ok (full tsim!)
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-- 2007-10-26 92 _tsim 0.26 9.2.02 J39 xc3s1000 d:ok (full tsim!)
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-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
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-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
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-- 2007-10-07 88 - 0.26 - - c:ok
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-- 2007-10-07 88 - 0.26 - - c:ok
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
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-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
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-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
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-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
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-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
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-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
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-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old
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-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old
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-- 'sta' behaviour with new 'stapc' command; rename
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-- 'sta' behaviour with new 'stapc' command; rename
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-- lal,lah -> wal,wah and implement locally; new
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-- lal,lah -> wal,wah and implement locally; new
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use work.simlib.all;
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use work.simlib.all;
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use work.simbus.all;
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use work.simbus.all;
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use work.pdp11_sim.all;
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use work.pdp11_sim.all;
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use work.pdp11.all;
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use work.pdp11.all;
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entity tb_pdp11_core is
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entity tb_pdp11core is
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end tb_pdp11_core;
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end tb_pdp11core;
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architecture sim of tb_pdp11_core is
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architecture sim of tb_pdp11core is
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signal CLK : slbit := '0';
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signal CLK : slbit := '0';
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signal RESET : slbit := '0';
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signal RESET : slbit := '0';
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signal UNUSEDSIGNAL : slbit := '0'; -- FIXME: hack to make ISim 11.3 happy
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signal UNUSEDSIGNAL : slbit := '0'; -- FIXME: hack to make ISim 11.3 happy
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signal CP_CNTL_req : slbit := '0';
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signal CP_CNTL_req : slbit := '0';
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CLK => CLK,
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CLK => CLK,
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CLK_CYCLE => SB_CLKCYCLE,
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CLK_CYCLE => SB_CLKCYCLE,
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CLK_STOP => CLK_STOP
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CLK_STOP => CLK_STOP
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);
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);
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UUT: entity work.tbd_pdp11_core
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UUT: entity work.tbd_pdp11core
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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CP_CNTL_req => CP_CNTL_req,
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CP_CNTL_req => CP_CNTL_req,
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CP_CNTL_func => CP_CNTL_func,
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CP_CNTL_func => CP_CNTL_func,
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CP_STAT_cpurust => CP_STAT_cpurust,
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CP_STAT_cpurust => CP_STAT_cpurust,
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CP_DOUT => CP_DOUT
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CP_DOUT => CP_DOUT
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);
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);
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proc_stim: process
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proc_stim: process
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file ifile : text open read_mode is "tb_pdp11_core_stim";
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file ifile : text open read_mode is "tb_pdp11core_stim";
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variable iline : line;
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variable iline : line;
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variable oline : line;
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variable oline : line;
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variable idelta : integer := 0;
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variable idelta : integer := 0;
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variable idummy : integer := 0;
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variable idummy : integer := 0;
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variable dcycle : integer := 0;
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variable dcycle : integer := 0;
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when ".merr " => -- .merr
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when ".merr " => -- .merr
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read_ea(iline, imerr);
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read_ea(iline, imerr);
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when ".anena" => -- .anena (ignore it)
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when ".anena" => -- .anena (ignore it)
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readempty(iline);
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readempty(iline);
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when ".cpmon" => -- .cpmon (ignore it)
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when ".rlmon" => -- .rlmon (ignore it)
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readempty(iline);
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readempty(iline);
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when ".rbmon" => -- .rbmon (ignore it)
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when ".rbmon" => -- .rbmon (ignore it)
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readempty(iline);
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readempty(iline);
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when ".scntl" => -- .scntl
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when ".scntl" => -- .scntl
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