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# $Id: INSTALL.txt 559 2014-06-06 21:26:47Z mueller $
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# $Id: INSTALL.txt 576 2014-08-02 12:24:28Z mueller $
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Guide to install and build w11a systems, test benches and support software
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Guide to install and build w11a systems, test benches and support software
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Table of content:
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Table of content:
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5. Compile and install the support software
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5. Compile and install the support software
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a. Compile sharable libraries
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a. Compile sharable libraries
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b. Setup Tcl packages
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b. Setup Tcl packages
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c. Rebuild Cypress FX2 firmware
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c. Rebuild Cypress FX2 firmware
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6. The build system
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6. The build system
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6 a. Setting up Xilinx environment with xtwi
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7. Building test benches
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7. Building test benches
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a. General instructions
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a. General instructions
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b. Available test benches
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b. Available test benches
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8. Building systems
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8. Building systems
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a. General instructions
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a. General instructions
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b. Configuring FPGAs
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b. Configuring FPGAs (via make flow)
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c. Available systems
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c. Configuring FPGAs (directly via config_wrapper)
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d. Available systems
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e. Available bitkits with bit and log files
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9. Generate Doxygen based source code view
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9. Generate Doxygen based source code view
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1. Download ---------------------------------------------------------------
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1. Download ---------------------------------------------------------------
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All instructions below assume that the project files reside in a
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All instructions below assume that the project files reside in a
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$XILINX/ghdl/unisim
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$XILINX/ghdl/unisim
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$XILINX/ghdl/simprim
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$XILINX/ghdl/simprim
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Two helper scripts will create these libraries:
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Two helper scripts will create these libraries:
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cd $RETROBASE
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cd $RETROBASE
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xilinx_ghdl_unisim
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xtwi xilinx_ghdl_unisim
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xilinx_ghdl_simprim
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xtwi xilinx_ghdl_simprim
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If you have several WebPack versions installed, repeat for each version.
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If you have several WebPack versions installed, repeat for each version.
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5. Compile and install the support software -------------------------------
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5. Compile and install the support software -------------------------------
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To build all sharable libraries
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To build all sharable libraries
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cd $RETROBASE/tools/src
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cd $RETROBASE/tools/src
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make -j 4
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make -j 4
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Default is to compile with -O2 and without -g. These options can be
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overwritten with the CXXOPTFLAGS enviromnent variable (or make opion).
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To build with -O3 optimize use
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make -j 4 CXXOPTFLAGS=-O3
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To build a debug version with full symbol table use
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make -j 4 CXXOPTFLAGS=-g
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To cleanup, e.g. before a re-build
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To cleanup, e.g. before a re-build
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cd $RETROBASE/tools/src
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cd $RETROBASE/tools/src
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rm_dep
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rm_dep
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make realclean
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make realclean
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Simulation and synthesis tools usually need a list of the VHDL source
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Simulation and synthesis tools usually need a list of the VHDL source
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files, often in proper compilation order (libraries before components).
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files, often in proper compilation order (libraries before components).
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The different tools have different formats of these 'project files'.
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The different tools have different formats of these 'project files'.
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The build system employed in this project is based on
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The build system employed in this project is based on manifest files called
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"VHDL bill of material" or 'vbom' files
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'vbom' or "VHDL bill of material" files
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which list for each vhdl source file the libraries and sources for
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which list for each vhdl source file the libraries and sources for the
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the instantiated components, the later via their vbom, and last but
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instantiated components, the later via their vbom, and last but not least
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not least the name of the vhdl source file. All file name are relative
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the name of the vhdl source file.
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to the current directory. A recursive traversal through all vbom's gives
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All file name are relative to the current directory. A recursive traversal
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for each vhld module all sources needed to compile it. The vbomconv script
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through all vbom's gives for each vhld module all sources needed to compile
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in tools/bin does this, and generates depending on options
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it. The vbomconv script in tools/bin does this, and generates depending on
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options
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- make dependency files
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- make dependency files
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- ISE xst project files
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- ISE xst project files
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- ISE ISim project files
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- ISE ISim project files
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- ghdl commands for analysis, inspection and make step
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- ghdl commands for analysis, inspection and make step
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The master make files contain pattern rules like
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The master make files contain pattern rules like
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%.ngc : %.vbom -- synthesize with xst
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%.ngc : %.vbom -- synthesize with xst
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% : %.vbom -- build functional model test bench
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% : %.vbom -- build functional model test bench
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which encapsulate all the vbomconf magic
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which encapsulate all the vbomconf magic
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A full w11a is build from more than 80 source files, test benches from
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A full w11a is build from about 100 source files, test benches from
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even more. Using the vbom's a large number of designs can be easily
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even more. Using the vbom's a large number of designs can be easily
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maintained.
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maintained.
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6a. Setting up Xilinx environment with xtwi --------------------------
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The Xilinx ISE setup script redefines PATH and LD_LIBRARY_PATH. The ISE
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tools run fine in this environment, but other installed programs on the
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system can (and actually do) fail.
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The build system uses a small wrapper script called xtwi to encapsulate
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the Xilinx environment. It expects that the environment variable XTWI_PATH
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is setup to the install path of the ISE version to be used. Without the
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/ISE_DS/ which is added by the ISE installation procedure !
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Note: don't run the ISE setup scripts ..../settings(32|64).sh in your
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working shell. Setup only XTWI_PATH !
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7. Building test benches --------------------------------------------------
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7. Building test benches --------------------------------------------------
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7a. General instructions ---------------------------------------------
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7a. General instructions ---------------------------------------------
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To compile a test bench named all is needed is
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To compile a test bench named all is needed is
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8. Building systems -------------------------------------------------------
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8. Building systems -------------------------------------------------------
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8a. General instructions ---------------------------------------------
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8a. General instructions ---------------------------------------------
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First ensure that XTWI_PATH is setup, see section 6a.
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To generate a bit file for a system named all is needed is
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To generate a bit file for a system named all is needed is
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make .bit
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make .bit
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The make file will use .vbom, create all make dependency files, build
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The make file will use .vbom, create all make dependency files, build
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For boards with a Cypress FX2 USB controller load the bitfile directly with
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For boards with a Cypress FX2 USB controller load the bitfile directly with
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make .jconfig
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make .jconfig
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If a svf file is required for configuring the FPGA a svf can be created
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from a bit file with
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make .svf
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If only the xst or par output is wanted just use
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If only the xst or par output is wanted just use
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make .ngc
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make .ngc
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make .ncd
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make .ncd
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make .mfsum
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make .mfsum
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after a re-build.
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after a re-build.
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8b. Configuring FPGAs ------------------------------------------------
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8b. Configuring FPGAs (via make flow) --------------------------------
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The make flow supports also loading the bitstream into FPGAs, either
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The make flow supports also loading the bitstream into FPGAs, either
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via Xilinx Impact, or via the Cypress FX2 USB controller is available.
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via Xilinx Impact, or via the Cypress FX2 USB controller is available.
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For Xilinx Impact a Xilinx USB Cable II has to be properly setup, than
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For Xilinx Impact a Xilinx USB Cable II has to be properly setup, than
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This will automatically check and optionaly re-load the FX2 firmware
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This will automatically check and optionaly re-load the FX2 firmware
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to a version matching the FPGA design, generate a .svf file from the
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to a version matching the FPGA design, generate a .svf file from the
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.bit file, and configure the FPGA. In case the bit file is out-of-date
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.bit file, and configure the FPGA. In case the bit file is out-of-date
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the whole design will be re-implemented before.
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the whole design will be re-implemented before.
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8c. Available systems ------------------------------------------------
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8c. Configuring FPGAs (directly via config_wrapper) ------------------
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The make flow described above uses two scripts
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config_wrapper # must be used with xtwi !
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fx2load_wrapper
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which can be used directly for loading available bit or svf files into
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the FPGA. For detailed documentation see the respective man pages.
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Examples for the supported boards are given in section 8e.
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8d. Available systems ------------------------------------------------
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Currently ready to build versions exist for
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Currently ready to build versions exist for
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- Digilent S3BOARD (-1000 FPGA version)
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- Digilent S3BOARD (-1000 FPGA version)
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- Digilent Nexys2 board (-1200 FPGA version)
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- Digilent Nexys2 board (-1200 FPGA version)
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- Digilent Nexys3 board
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- Digilent Nexys3 board
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Tarballs with ready to use bit file and and all logfiles from the tool
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chain can be downloaded from
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http://www.retro11.de/data/oc_w11/bitkits/
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This area is organized in folders for different releases. The tarball
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file names contain information about release, Xlinix tool, and design:
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__.tgz
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To build the designs locally use
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To build the designs locally use
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1. rlink tester
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1. rlink tester
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a. for Digilent S3BOARD
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a. for Digilent S3BOARD
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c. for Digilent Nexys3 board
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c. for Digilent Nexys3 board
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cd $RETROBASE/rtl/sys_gen/w11a/nexys3
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cd $RETROBASE/rtl/sys_gen/w11a/nexys3
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make sys_w11a_n3.bit
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make sys_w11a_n3.bit
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8e. Available bitkits with bit and log files -------------------------
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Tarballs with ready to use bit files and all logfiles from the tool
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chain can be downloaded from
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http://www.retro11.de/data/oc_w11/bitkits/
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This area is organized in folders for different releases. The tarball
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file names contain information about release, Xlinix tool, and design:
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__.tgz
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These designs can be loaded with config_wrapper into the FPGA. The
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procedures for the supported boards are given below.
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Notes:
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1. XTWI_PATH and RETROBASE environment variables must be defined.
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2. config_wrapper bit2svf is only needed once to create the svf files.
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3. fx2load_wrapper is needed once after each board power on.
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a. for Digilent S3BOARD (using ISE Impact)
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xtwi config_wrapper --board=s3board iconfig .bit
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b. for Digilent Nexys2 board (using Cypress FX2 USB controller)
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xtwi config_wrapper --board=nexys2 bit2svf .bit
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fx2load_wrapper --board=nexys2 --file=nexys2_jtag_2fifo_ic.ihx
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xtwi config_wrapper --board=nexys2 jconfig .svf
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c. for Digilent Nexys3 board (using Cypress FX2 USB controller)
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xtwi config_wrapper --board=nexys3 bit2svf .bit
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fx2load_wrapper --board=nexys3 --file=nexys3_jtag_2fifo_ic.ihx
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xtwi config_wrapper --board=nexys3 jconfig .svf
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9. Generate Doxygen based source code view --------------------------------
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9. Generate Doxygen based source code view --------------------------------
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Currently there is not much real documentation included in the source
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Currently there is not much real documentation included in the source
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files. The doxygen generated html output is nevertheless very useful
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files. The doxygen generated html output is nevertheless very useful
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to browse the code. C++, Tcl and Vhdl source are covered by setup files
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to browse the code. C++, Tcl and Vhdl source are covered by setup files
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