| Line 1... |
Line 1... |
# $Id: w11a_tb_guide.txt 547 2013-12-29 13:10:07Z mueller $
|
# $Id: w11a_tb_guide.txt 578 2014-08-05 21:28:19Z mueller $
|
|
|
Guide to running w11a test benches
|
Guide to running w11a test benches
|
|
|
Table of content:
|
Table of content:
|
|
|
| Line 66... |
Line 66... |
time tbw tb_serport_uart_rx |\
|
time tbw tb_serport_uart_rx |\
|
tee tb_serport_uart_rx_dsim.log | egrep "(FAIL|DONE)"
|
tee tb_serport_uart_rx_dsim.log | egrep "(FAIL|DONE)"
|
-> 1269955.0 ns 63488: DONE
|
-> 1269955.0 ns 63488: DONE
|
-> real 0m01.178s user 0m01.172s sys 0m00.020s
|
-> real 0m01.178s user 0m01.172s sys 0m00.020s
|
|
|
|
|
- serport receiver/transmitter test
|
- serport receiver/transmitter test
|
make tb_serport_uart_rxtx
|
make tb_serport_uart_rxtx
|
time tbw tb_serport_uart_rxtx |\
|
time tbw tb_serport_uart_rxtx |\
|
tee tb_serport_uart_rxtx_dsim.log | egrep "(FAIL|DONE)"
|
tee tb_serport_uart_rxtx_dsim.log | egrep "(FAIL|DONE)"
|
-> 52335.0 ns 2607: DONE
|
-> 52335.0 ns 2607: DONE
|
| Line 99... |
Line 98... |
time tbw tb_rlink_sp1c tb_rlink_sp1c_stim.dat |\
|
time tbw tb_rlink_sp1c tb_rlink_sp1c_stim.dat |\
|
tee tb_rlink_sp1c_stim2_dsim.log | egrep "(FAIL|DONE)"
|
tee tb_rlink_sp1c_stim2_dsim.log | egrep "(FAIL|DONE)"
|
-> 24695.0 ns 1225: DONE
|
-> 24695.0 ns 1225: DONE
|
-> real 0m0.133s user 0m0.104s sys 0m0.008s
|
-> real 0m0.133s user 0m0.104s sys 0m0.008s
|
|
|
|
|
time tbw tb_rlink_sp1c tb_rlink_stim.dat |\
|
time tbw tb_rlink_sp1c tb_rlink_stim.dat |\
|
tee tb_rlink_sp1c_dsim.log | egrep "(FAIL|DONE)"
|
tee tb_rlink_sp1c_dsim.log | egrep "(FAIL|DONE)"
|
-> 551935.0 ns 27587: DONE
|
-> 551935.0 ns 27587: DONE
|
-> real 0m01.714s user 0m01.704s sys 0m00.044s
|
-> real 0m01.714s user 0m01.704s sys 0m00.044s
|
|
|
| Line 111... |
Line 109... |
|
|
cd $RETROBASE/rtl/w11a/tb
|
cd $RETROBASE/rtl/w11a/tb
|
make tb_pdp11core
|
make tb_pdp11core
|
time tbw tb_pdp11core |\
|
time tbw tb_pdp11core |\
|
tee tb_pdp11core_dsim.log | egrep "(FAIL|DONE)"
|
tee tb_pdp11core_dsim.log | egrep "(FAIL|DONE)"
|
-> 1220255.0 ns 61003: DONE
|
-> 1220255.0 ns 61073: DONE
|
-> real 0m10.736s user 0m10.713s sys 0m00.060s
|
-> real 0m10.736s user 0m10.713s sys 0m00.060s
|
|
|
- w11a core test (using post-synthesis model)
|
- w11a core test (using post-synthesis model)
|
|
|
make ghdl_tmp_clean tb_pdp11core_ssim
|
make ghdl_tmp_clean && make tb_pdp11core_ssim
|
time tbw tb_pdp11core_ssim |\
|
time tbw tb_pdp11core_ssim |\
|
tee tb_pdp11core_ssim.log | egrep "(FAIL|DONE)"
|
tee tb_pdp11core_ssim.log | egrep "(FAIL|DONE)"
|
-> 1220255.0 ns 61003: DONE
|
-> 1220255.0 ns 61073: DONE
|
-> real 1m09.738s user 1m09.588s sys 0m00.096s
|
-> real 1m09.738s user 1m09.588s sys 0m00.096s
|
|
|
- s3board sram controller test
|
- s3board sram controller test
|
|
|
cd $RETROBASE/rtl/bplib/s3board/tb
|
cd $RETROBASE/rtl/bplib/s3board/tb
|
| Line 131... |
Line 129... |
time tbw tb_s3_sram_memctl |\
|
time tbw tb_s3_sram_memctl |\
|
tee tb_s3_sram_memctl_dsim.log | egrep "(FAIL|DONE)"
|
tee tb_s3_sram_memctl_dsim.log | egrep "(FAIL|DONE)"
|
-> 5015.0 ns 241: DONE
|
-> 5015.0 ns 241: DONE
|
-> real 0m00.113s user 0m00.068s sys 0m00.016s
|
-> real 0m00.113s user 0m00.068s sys 0m00.016s
|
|
|
|
|
- nexys2/nexys3 cram controller test
|
- nexys2/nexys3 cram controller test
|
|
|
cd $RETROBASE/rtl/bplib/nxcramlib/tb
|
cd $RETROBASE/rtl/bplib/nxcramlib/tb
|
make tb_nx_cram_memctl_as
|
make tb_nx_cram_memctl_as
|
time tbw tb_nx_cram_memctl_as |\
|
time tbw tb_nx_cram_memctl_as |\
|
tee tb_nx_cram_memctl_as_dsim.log | egrep "(FAIL|DONE)"
|
tee tb_nx_cram_memctl_as_dsim.log | egrep "(FAIL|DONE)"
|
-> 24272.5 ns 1204: DONE
|
-> 24272.5 ns 1204: DONE
|
-> real 0m00.343s user 0m00.248s sys 0m00.100s
|
-> real 0m00.343s user 0m00.248s sys 0m00.100s
|
|
|
|
|
3. System tests benches ---------------------------------------------------
|
3. System tests benches ---------------------------------------------------
|
|
|
The system tests allow to verify to verify a full system design.
|
The system tests allow to verify to verify a full system design.
|
In this case vhdl test bench code contains
|
In this case vhdl test bench code contains
|
- (simple) models of the memories used on the FPGA boards
|
- (simple) models of the memories used on the FPGA boards
|
| Line 250... |
Line 246... |
make tb_w11a_s3
|
make tb_w11a_s3
|
time ti_rri --pack=rw11 --run="tbw tb_w11a_s3" --fifo --logl=3 -- \
|
time ti_rri --pack=rw11 --run="tbw tb_w11a_s3" --fifo --logl=3 -- \
|
"rw11::setup_cpu" \
|
"rw11::setup_cpu" \
|
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
|
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
|
tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
|
tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
|
-> 10225140.0 ns 511247: DONE
|
-> 7328980.0 ns 366439: DONE
|
-> real 0m52.105s user 0m51.871s sys 0m0.376s
|
-> real 0m45.225s user 0m43.631s sys 0m0.400s
|
|
|
- sys_w11a_n2 test bench
|
- sys_w11a_n2 test bench
|
|
|
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
|
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
|
make tb_w11a_n2
|
make tb_w11a_n2
|
time ti_rri --pack=rw11 --run="tbw tb_w11a_n2" --fifo --logl=3 -- \
|
time ti_rri --pack=rw11 --run="tbw tb_w11a_n2" --fifo --logl=3 -- \
|
"rw11::setup_cpu" \
|
"rw11::setup_cpu" \
|
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
|
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
|
tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
|
tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
|
-> 10278380.0 ns 513908: DONE
|
-> 7372840.0 ns 368631: DONE
|
-> real 1m2.951s user 1m2.628s sys 0m0.532s
|
-> real 0m55.536s user 0m52.967s sys 0m0.520s
|
|
|
- sys_w11a_n3 test bench
|
- sys_w11a_n3 test bench
|
|
|
cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
|
cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
|
make tb_w11a_n3
|
make tb_w11a_n3
|
time ti_rri --pack=rw11 --run="tbw tb_w11a_n3" --fifo --logl=3 -- \
|
time ti_rri --pack=rw11 --run="tbw tb_w11a_n3" --fifo --logl=3 -- \
|
"rw11::setup_cpu" \
|
"rw11::setup_cpu" \
|
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
|
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
|
tee tb_w11a_n3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
|
tee tb_w11a_n3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
|
-> 5167410.0 ns 516720: DONE
|
-> 5121571.1 ns 368738: DONE
|
-> real 1m5.322s user 1m5.072s sys 0m0.500s
|
-> real 0m54.908s user 0m51.831s sys 0m0.512s
|
|
|
A new, modular w11a test bench is under construction. So far it is very
|
A new, modular w11a test bench is under construction. So far it is very
|
incomplete. This very preliminary version can be executed with
|
incomplete. This very preliminary version can be executed with
|
|
|
- sys_w11a_n2 test bench
|
- sys_w11a_n2 test bench
|
| Line 285... |
Line 281... |
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
|
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
|
make tb_w11a_n2
|
make tb_w11a_n2
|
time ti_rri --pack=rw11 --run="tbw tb_w11a_n2" --fifo --logl=3 -- \
|
time ti_rri --pack=rw11 --run="tbw tb_w11a_n2" --fifo --logl=3 -- \
|
"rw11::setup_cpu" "rw11::tbench @w11a_all.dat" | \
|
"rw11::setup_cpu" "rw11::tbench @w11a_all.dat" | \
|
tee w11a_tbench_dsim.log | egrep "(-[EFW]:|FAIL|PASS|DONE)"
|
tee w11a_tbench_dsim.log | egrep "(-[EFW]:|FAIL|PASS|DONE)"
|
-> 904180.0 ns 45198: DONE
|
-> 5019660.0 ns 250972: DONE
|
-> real 0m5.539s user 0m5.748s sys 0m0.204s
|
-> real 0m32.501s user 0m31.082s sys 0m0.500s
|
|
|
