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-- $Id: is61lv25616al.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: is61lv25616al.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- the trailing edge of we.
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-- the trailing edge of we.
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-19 427 1.0.2 now numeric_std clean
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-- 2008-05-12 145 1.0.1 BUGFIX: Output now 'Z' if byte enables deasserted
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-- 2008-05-12 145 1.0.1 BUGFIX: Output now 'Z' if byte enables deasserted
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-- 2007-12-14 101 1.0 Initial version (written on warsaw airport)
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-- 2007-12-14 101 1.0 Initial version (written on warsaw airport)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Truth table accoring to data sheet:
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-- Truth table accoring to data sheet:
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--
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--
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-- L L X H L high-Z D_in
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-- L L X H L high-Z D_in
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-- L L X L L D_in D_in
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-- L L X L L D_in D_in
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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entity is61lv25616al is -- ISSI 61LV25612AL SRAM model
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entity is61lv25616al is -- ISSI 61LV25612AL SRAM model
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port (
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port (
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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entity is61lv25616al_bank is -- ISSI 61LV25612AL bank
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entity is61lv25616al_bank is -- ISSI 61LV25612AL bank
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port (
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port (
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proc_sram: process (CE, OE, WE, BE, WE_EFF, ADDR, DATA)
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proc_sram: process (CE, OE, WE, BE, WE_EFF, ADDR, DATA)
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variable ram : ram_type := (others=>datzero);
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variable ram : ram_type := (others=>datzero);
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begin
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begin
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if WE_EFF'event and WE_EFF='0' then -- end of write cycle
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if falling_edge(WE_EFF) then -- end of write cycle
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-- note: to_x01 used below to prevent
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-- note: to_x01 used below to prevent
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-- that 'z' a written into mem.
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-- that 'z' a written into mem.
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ram(conv_integer(unsigned(ADDR))) := to_x01(DATA);
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ram(to_integer(unsigned(ADDR))) := to_x01(DATA);
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end if;
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end if;
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if CE='1' and OE='1' and BE='1' and WE='0' then -- output driver
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if CE='1' and OE='1' and BE='1' and WE='0' then -- output driver
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DATA <= ram(conv_integer(unsigned(ADDR)));
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DATA <= ram(to_integer(unsigned(ADDR)));
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else
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else
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DATA <= (others=>'Z');
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DATA <= (others=>'Z');
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end if;
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end if;
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end process proc_sram;
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end process proc_sram;
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