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-- $Id: n2_cram_memctl_as.vhd 427 2011-11-19 21:04:11Z mueller $
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-- $Id: nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $
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--
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--
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: n2_cram_memctl_as - syn
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-- Module Name: nx_cram_memctl_as - syn
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-- Description: nexys2: CRAM driver - async and page mode
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-- Description: nexys2/3: CRAM driver - async and page mode
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--
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--
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-- Dependencies: vlib/xlib/iob_reg_o
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-- Dependencies: vlib/xlib/iob_reg_o
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-- vlib/xlib/iob_reg_o_gen
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-- vlib/xlib/iob_reg_o_gen
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-- vlib/xlib/iob_reg_io_gen
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-- vlib/xlib/iob_reg_io_gen
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-- Test bench: tb/tb_n2_cram_memctl
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-- Test bench: tb/tb_nx_cram_memctl_as
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-- fw_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
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-- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 11.4, 13.1; ghdl 0.26
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-- Tool versions: xst 11.4, 13.1; ghdl 0.26
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
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-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
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-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
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-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-26 433 1.2 renamed from n2_cram_memctl_as
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-- 2011-11-19 432 1.1 remove O_FLA_CE_N port
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-- 2011-11-19 427 1.0.5 now numeric_std clean
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-- 2011-11-19 427 1.0.5 now numeric_std clean
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-- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics
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-- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics
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-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
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-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
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-- cycle;
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-- cycle;
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-- 2010-05-30 297 1.0.2 use READ(0|1)DELAY generic
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-- 2010-05-30 297 1.0.2 use READ(0|1)DELAY generic
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.xlib.all;
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use work.xlib.all;
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entity n2_cram_memctl_as is -- CRAM driver (async+page mode)
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entity nx_cram_memctl_as is -- CRAM driver (async+page mode)
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generic (
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generic (
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READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
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READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
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READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
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READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
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WRITEDELAY : positive := 3); -- write delay in clock cycles
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WRITEDELAY : positive := 3); -- write delay in clock cycles
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port (
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port (
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CLK : out slbit; -- cram: clock
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O_MEM_CRE : out slbit; -- cram: command register enable
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O_MEM_CRE : out slbit; -- cram: command register enable
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I_MEM_WAIT : in slbit; -- cram: mem wait
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I_MEM_WAIT : in slbit; -- cram: mem wait
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O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
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O_MEM_ADDR : out slv23; -- cram: address lines
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O_MEM_ADDR : out slv23; -- cram: address lines
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IO_MEM_DATA : inout slv16 -- cram: data lines
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IO_MEM_DATA : inout slv16 -- cram: data lines
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);
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);
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end n2_cram_memctl_as;
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end nx_cram_memctl_as;
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architecture syn of n2_cram_memctl_as is
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architecture syn of nx_cram_memctl_as is
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type state_type is (
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type state_type is (
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s_idle, -- s_idle: wait for req
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s_idle, -- s_idle: wait for req
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s_rdinit, -- s_rdinit: read init cycle
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s_rdinit, -- s_rdinit: read init cycle
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s_rdwait0, -- s_rdwait0: read wait low word
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s_rdwait0, -- s_rdwait0: read wait low word
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);
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);
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O_MEM_ADV_N <= '0';
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O_MEM_ADV_N <= '0';
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O_MEM_CLK <= '0';
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O_MEM_CLK <= '0';
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O_MEM_CRE <= '0';
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O_MEM_CRE <= '0';
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O_FLA_CE_N <= '1';
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if rising_edge(CLK) then
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if rising_edge(CLK) then
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