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-- $Id: ibd_kw11l.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: ibd_kw11l.vhd 335 2010-10-24 22:24:23Z mueller $
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--
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--
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-- Copyright 2008-2009 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Description: ibus dev(loc): KW11-L (line clock)
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-- Description: ibus dev(loc): KW11-L (line clock)
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-10-17 333 12.1 M53 xc3s1000-4 9 23 0 14 s 5.3
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-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 8 25 0 15 s 5.3
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-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 8 25 0 15 s 5.3
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-10-17 333 1.1 use ibus V2 interface
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-- 2009-06-01 221 1.0.5 BUGFIX: add RESET; don't clear tcnt on ibus reset
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-- 2009-06-01 221 1.0.5 BUGFIX: add RESET; don't clear tcnt on ibus reset
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-- 2008-08-22 161 1.0.4 use iblib; add EI_ACK to proc_next sens. list
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-- 2008-08-22 161 1.0.4 use iblib; add EI_ACK to proc_next sens. list
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-- 2008-05-09 144 1.0.3 use intreq flop, use EI_ACK
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-- 2008-05-09 144 1.0.3 use intreq flop, use EI_ACK
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-- 2008-01-20 112 1.0.2 fix proc_next sensitivity list; use BRESET
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-- 2008-01-20 112 1.0.2 fix proc_next sensitivity list; use BRESET
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-- 2008-01-06 111 1.0.1 Renamed to ibd_kw11l (RRI_REQ not used)
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-- 2008-01-06 111 1.0.1 Renamed to ibd_kw11l (RRI_REQ not used)
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constant twidth : natural := 5;
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constant twidth : natural := 5;
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constant tdivide : natural := 20;
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constant tdivide : natural := 20;
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type regs_type is record -- state registers
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type regs_type is record -- state registers
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ibsel : slbit; -- ibus select
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ie : slbit; -- interrupt enable
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ie : slbit; -- interrupt enable
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moni : slbit; -- monitor bit
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moni : slbit; -- monitor bit
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intreq : slbit; -- interrupt request
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intreq : slbit; -- interrupt request
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tcnt : slv(twidth-1 downto 0); -- timer counter
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tcnt : slv(twidth-1 downto 0); -- timer counter
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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'0', -- ibsel
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'0', -- ie
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'0', -- ie
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'1', -- moni (set on reset !!)
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'1', -- moni (set on reset !!)
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'0', -- intreq
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'0', -- intreq
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(others=>'0') -- tcnt
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(others=>'0') -- tcnt
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);
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);
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end process proc_regs;
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end process proc_regs;
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proc_next : process (R_REGS, IB_MREQ, CE_MSEC, EI_ACK)
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proc_next : process (R_REGS, IB_MREQ, CE_MSEC, EI_ACK)
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable ibsel : slbit := '0';
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variable idout : slv16 := (others=>'0');
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variable idout : slv16 := (others=>'0');
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variable ibreq : slbit := '0';
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variable ibw0 : slbit := '0';
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begin
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begin
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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ibsel := '0';
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idout := (others=>'0');
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idout := (others=>'0');
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ibreq := IB_MREQ.re or IB_MREQ.we;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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-- ibus address decoder
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-- ibus address decoder
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if IB_MREQ.req='1' and IB_MREQ.addr=ibaddr_kw11l(12 downto 1) then
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n.ibsel := '0';
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ibsel := '1';
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if IB_MREQ.aval='1' and
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IB_MREQ.addr=ibaddr_kw11l(12 downto 1) then
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n.ibsel := '1';
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end if;
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end if;
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-- ibus output driver
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-- ibus output driver
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if ibsel = '1' then
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if r.ibsel = '1' then
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idout(lks_ibf_ie) := R_REGS.ie;
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idout(lks_ibf_ie) := R_REGS.ie;
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idout(lks_ibf_moni) := R_REGS.moni;
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idout(lks_ibf_moni) := R_REGS.moni;
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end if;
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end if;
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-- ibus write transactions
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-- ibus write transactions
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if ibsel='1' and IB_MREQ.we='1' and IB_MREQ.be0='1' then
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if r.ibsel='1' and ibw0='1' then
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n.ie := IB_MREQ.din(lks_ibf_ie);
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n.ie := IB_MREQ.din(lks_ibf_ie);
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n.moni := IB_MREQ.din(lks_ibf_moni);
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n.moni := IB_MREQ.din(lks_ibf_moni);
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if IB_MREQ.din(lks_ibf_ie)='0' or IB_MREQ.din(lks_ibf_moni)='0' then
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if IB_MREQ.din(lks_ibf_ie)='0' or IB_MREQ.din(lks_ibf_moni)='0' then
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n.intreq := '0';
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n.intreq := '0';
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end if;
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end if;
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end if;
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end if;
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N_REGS <= n;
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N_REGS <= n;
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IB_SRES.dout <= idout;
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IB_SRES.dout <= idout;
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IB_SRES.ack <= ibsel;
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IB_SRES.ack <= r.ibsel and ibreq;
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IB_SRES.busy <= '0';
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IB_SRES.busy <= '0';
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EI_REQ <= r.intreq;
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EI_REQ <= r.intreq;
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end process proc_next;
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end process proc_next;
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