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-- $Id: ibdr_rhrp.vhd 680 2015-05-14 13:29:46Z mueller $
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-- $Id: ibdr_rhrp.vhd 682 2015-05-15 18:35:29Z mueller $
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--
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--
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-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- 2015-05-14 680 14.7 131013 xc6slx16-2 211 408 8 131 s 8.8
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-- 2015-05-14 680 14.7 131013 xc6slx16-2 211 408 8 131 s 8.8
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-- 2015-04-06 664 14.7 131013 xc6slx16-2 177 331 8 112 s 8.7
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-- 2015-04-06 664 14.7 131013 xc6slx16-2 177 331 8 112 s 8.7
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2015-05-15 682 1.0.1 correct ibsel range select logic
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-- 2015-05-14 680 1.0 Initial version
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-- 2015-05-14 680 1.0 Initial version
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-- 2015-03-15 658 0.1 First draft
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-- 2015-03-15 658 0.1 First draft
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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variable ieunit : slv2 := (others=>'0');
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variable ieunit : slv2 := (others=>'0');
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variable iomux : slv4 := (others=>'0'); -- omux select
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variable iomux : slv4 := (others=>'0'); -- omux select
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variable iamap : slv5 := (others=>'0'); -- mem mapped address
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variable iamap : slv5 := (others=>'0'); -- mem mapped address
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variable imask : slv16 := (others=>'0'); -- implemented bits mask
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variable imask : slv16 := (others=>'0'); -- implemented bits mask
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variable inxr : slbit := '0'; -- non-existent register
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variable imbreg : slbit := '0'; -- massbus register
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variable imbreg : slbit := '0'; -- massbus register
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variable inormr : slbit := '0'; -- inhibit rmr protect
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variable inormr : slbit := '0'; -- inhibit rmr protect
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variable idte : slv3 := (others=>'0'); -- encoded drive type
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variable idte : slv3 := (others=>'0'); -- encoded drive type
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variable idtyp : slv6 := (others=>'0'); -- drive type (5:0)
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variable idtyp : slv6 := (others=>'0'); -- drive type (5:0)
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ieunit := (others=>'0');
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ieunit := (others=>'0');
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iomux := (others=>'0');
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iomux := (others=>'0');
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iamap := (others=>'0');
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iamap := (others=>'0');
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imask := (others=>'1'); -- default: all bits ok
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imask := (others=>'1'); -- default: all bits ok
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inxr := '0';
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imbreg := '0';
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imbreg := '0';
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inormr := '0';
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inormr := '0';
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idte := (others=>'0');
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idte := (others=>'0');
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idtyp := (others=>'0');
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idtyp := (others=>'0');
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-- ibus address decoder, accept only offsets 0 to ibaddr_cs3
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-- ibus address decoder, accept only offsets 0 to ibaddr_cs3
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n.ibsel := '0';
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n.ibsel := '0';
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if IB_MREQ.aval = '1' and
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if IB_MREQ.aval = '1' and
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IB_MREQ.addr(12 downto 6) = ibaddr_rhrp(12 downto 6) and
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IB_MREQ.addr(12 downto 6) = ibaddr_rhrp(12 downto 6) and
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unsigned(ibaddr_rhrp(5 downto 0)) <= unsigned(ibaddr_cs3) then
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unsigned(IB_MREQ.addr(5 downto 1)) <= unsigned(ibaddr_cs3) then
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n.ibsel := '1';
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n.ibsel := '1';
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end if;
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end if;
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-- internal state machine
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-- internal state machine
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case r.state is
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case r.state is
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iomux := omux_bae;
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iomux := omux_bae;
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when ibaddr_cs3 => -- RxCS3 control reg 3
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when ibaddr_cs3 => -- RxCS3 control reg 3
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iomux := omux_cs3;
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iomux := omux_cs3;
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when others => -- unknown register
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when others => null; -- doesn't happen, ibsel only for
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inxr := '1';
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-- subrange up to cs3, and all
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-- 22 regs are decoded above
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end case; -- case IB_MREQ.addr
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end case; -- case IB_MREQ.addr
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n.amap := iamap;
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n.amap := iamap;
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n.omux := iomux;
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n.omux := iomux;
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n.dinmsk := imask and IB_MREQ.din;
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n.dinmsk := imask and IB_MREQ.din;
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n.state := s_setrmr;
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n.state := s_setrmr;
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end if;
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end if;
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end if;
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end if;
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elsif IB_MREQ.re = '1' then -- read request
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elsif IB_MREQ.re = '1' then -- read request
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if inxr = '1' then -- unknown register
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ibreq := '0'; -- suppress ack & hold --> ibus err
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else
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if ibrem='0' and imbreg='1' and ined='1' then
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if ibrem='0' and imbreg='1' and ined='1' then
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n.cs2ned := '1'; -- signal error
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n.cs2ned := '1'; -- signal error
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else
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else
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ibhold := '1';
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ibhold := '1';
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n.state := s_read;
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n.state := s_read;
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end if;
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end if;
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end if;
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end if; -- if IB_MREQ.we .. elsif IB_MREQ.re
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end if; -- if IB_MREQ.we .. elsif IB_MREQ.re
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-- BRESET and ITIMER can be handled in the 'else' because both can
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-- BRESET and ITIMER can be handled in the 'else' because both can
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-- never come during an ibus transaction. Done here to keep logic
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-- never come during an ibus transaction. Done here to keep logic
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