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FLOWTYPE = FPGA_SYNTHESIS;
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FLOWTYPE = FPGA_SYNTHESIS;
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#########################################################
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## Filename: xst_vhdl.opt
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##
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## VHDL Option File for XST targeted for speed
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## This works for FPGA devices.
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##
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## Version: 8.1.1
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## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/optionfiles/fpga_xst_vhdl_speed.opt,v 1.13 2004/10/01 22:29:20 rvklair Exp $
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#########################################################
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# Options for XST
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#
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#
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# $Id: syn_s3_speed.opt 405 2011-08-14 08:16:28Z mueller $
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#
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# Revision History:
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# Date Rev Version Comment
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# 2011-08-13 405 1.1 renamed, moved to rtl/make;
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# 2007-07-20 67 1.0 Initial version
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#
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# Derived from ISE xst_vhdl.opt
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#
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#
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# ----------------------------------------------------------------------------
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# Options for XST
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#
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#
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Program xst
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Program xst
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-ifn _xst.scr; # input XST script file
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-ifn _xst.scr; # input XST script file
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-ofn _xst.log; # output XST log file
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-ofn _xst.log; # output XST log file
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-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
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-intstyle xflow; # Message Reporting Style
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#
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#
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# The options listed under ParamFile are the XST Properties that can be set by the
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# ParamFile lists the XST Properties that can be set by the user.
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# user. To turn on an option, uncomment by removing the '#' in front of the switch.
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#
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#
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ParamFile: _xst.scr
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ParamFile: _xst.scr
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"run";
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"run";
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#
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#
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# Global Synthesis Options
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# Global Synthesis Options
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#
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#
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"-ifn "; # Input/Project File Name
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"-ifn "; # Input/Project File Name
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"-ifmt VHDL"; # Input Format
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"-ifmt VHDL"; # Input Format (Verilog or VHDL)
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"-ofn "; # Output File Name
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"-ofn "; # Output File Name
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"-ofmt ngc"; # Output File Format
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"-ofmt ngc"; # Output File Format
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"-p "; # Target Device
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"-p "; # Target Device
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"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
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"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
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"-opt_level 2";
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"-opt_level 2"; # Optimization Effort Criteria: 2=High
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"-uc .xcf"; # Constraint File name
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"-uc .xcf"; # Constraint File name
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#"-case maintain"; # Specifies how to handle source name case
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# upper, lower
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#"-keep_hierarchy NO"; # Prevents optimization across module boundaries
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# CPLD default YES, FPGA default NO
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#"-write_timing_constraints NO"; # Write Timing Constraints
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# YES, NO
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#"-cross_clock_analysis NO"; # Cross Clock Option
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# YES, NO
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#"-iobuf YES"; # Add I/O Buffers to top level portS
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# YES, NO
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#
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#
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# The following are HDL Options
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# The following are HDL Options
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#
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#
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# The following are Xilinx FPGA specific options for Virtex, VirtexE, Virtex-II and Spartan2
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#
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#"-register_balancing NO"; # Register Balancing
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# YES, NO, Forward, Backward
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#"-move_first_stage YES"; # Move First Flip-Flop Stage
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# YES, NO
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#"-move_last_stage YES"; # Move Last Flip-Flop Stage
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# YES, NO
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End ParamFile
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End ParamFile
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End Program xst
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End Program xst
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#
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#
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# See XST USER Guide Chapter 8 (Command Line Mode) for all XST options
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#
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