URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.7/] [rtl/] [make_ise/] [syn_s6_speed.opt] - Diff between revs 12 and 17

Rev 12	Rev 17
Line 1...	Line 1...
`FLOWTYPE = FPGA_SYNTHESIS;`	`FLOWTYPE = FPGA_SYNTHESIS;`
`#`	`#`
`# $Id: syn_s6_speed.opt 405 2011-08-14 08:16:28Z mueller $`	`# $Id: syn_s6_speed.opt 456 2012-02-05 22:19:44Z mueller $`
`#`	`#`
`# Revision History:`	`# Revision History:`
`# Date Rev Version Comment`	`# Date Rev Version Comment`
	`# 2012-02-05 456 1.1 use $top_entity variable for -top attribute`
`# 2011-08-13 405 1.0 Initial version`	`# 2011-08-13 405 1.0 Initial version`
`#`	`#`
`# Derived from ISE xst_mixed.opt`	`# Derived from ISE xst_mixed.opt`
`#`	`#`
`# ----------------------------------------------------------------------------`	`# ----------------------------------------------------------------------------`
Line 25...	Line 26...
`#`	`#`
`"-ifn "; # Input/Project File Name`	`"-ifn "; # Input/Project File Name`
`"-ifmt mixed"; # Input Format (Verilog and VHDL)`	`"-ifmt mixed"; # Input Format (Verilog and VHDL)`
`"-ofn "; # Output File Name`	`"-ofn "; # Output File Name`
`"-ofmt ngc"; # Output File Format`	`"-ofmt ngc"; # Output File Format`
`"-top "; # Top Design Name`	`"-top $top_entity"; # Top Design Name`
`"-p "; # Target Device`	`"-p "; # Target Device`
`"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED`	`"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED`
`"-opt_level 2"; # Optimization Effort Criteria: 2=High`	`"-opt_level 2"; # Optimization Effort Criteria: 2=High`
`"-uc .xcf"; # Constraint File name`	`"-uc .xcf"; # Constraint File name`
`#`	`#`