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-- $Id: sys_tst_serloop2_n2.vhd 441 2011-12-20 17:01:16Z mueller $
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-- $Id: sys_tst_serloop2_n2.vhd 444 2011-12-25 10:04:58Z mueller $
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--
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--
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- 2011-11-16 426 13.1 O40d xc3s1200e-4 494 661 64 547 t xx.x
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-- 2011-11-16 426 13.1 O40d xc3s1200e-4 494 661 64 547 t xx.x
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-- 2011-11-13 425 13.1 O40d xc3s1200e-4 487 645 64 532 t xx.x
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-- 2011-11-13 425 13.1 O40d xc3s1200e-4 487 645 64 532 t xx.x
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-12-23 444 1.1 remove clksys output hack
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-- 2011-12-09 437 1.0.4 rename serport stat->moni port
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-- 2011-12-09 437 1.0.4 rename serport stat->moni port
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-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
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-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
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-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
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-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
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-- 2011-11-17 426 1.0.1 use dcm_sfs now
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-- 2011-11-17 426 1.0.1 use dcm_sfs now
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-- 2011-11-12 423 1.0 Initial version
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-- 2011-11-12 423 1.0 Initial version
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entity sys_tst_serloop2_n2 is -- top level
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entity sys_tst_serloop2_n2 is -- top level
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-- implements nexys2_fusp_aif
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-- implements nexys2_fusp_aif
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port (
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port (
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I_CLK50 : in slbit; -- 50 MHz clock
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I_CLK50 : in slbit; -- 50 MHz clock
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O_CLKSYS : out slbit; -- DCM derived system clock
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I_RXD : in slbit; -- receive data (board view)
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- n2 switches
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I_SWI : in slv8; -- n2 switches
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I_BTN : in slv4; -- n2 buttons
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I_BTN : in slv4; -- n2 buttons
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O_LED : out slv8; -- n2 leds
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O_LED : out slv8; -- n2 leds
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CLKIN => I_CLK50,
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CLKIN => I_CLK50,
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CLKFX => CLK,
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CLKFX => CLK,
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LOCKED => open
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LOCKED => open
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);
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);
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O_CLKSYS <= '0';
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CLKDIV_U : clkdivce
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CLKDIV_U : clkdivce
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generic map (
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generic map (
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CDUWIDTH => 7,
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CDUWIDTH => 7,
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USECDIV => sys_conf_clkudiv_usecdiv, -- syn: 100 sim: 20
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USECDIV => sys_conf_clkudiv_usecdiv, -- syn: 100 sim: 20
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MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
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MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
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