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-- $Id: memlib.vhd 389 2011-07-07 21:59:00Z mueller $
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-- $Id: memlib.vhd 424 2011-11-13 16:38:23Z mueller $
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--
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--
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-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Package Name: memlib
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-- Package Name: memlib
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-- Description: Basic memory components: single/dual port synchronous and
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-- Description: Basic memory components: single/dual port synchronous and
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-- asynchronus rams; Fifo's.
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-- asynchronus rams; Fifo's.
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim
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-- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim
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-- 2008-03-02 122 1.0.2 change generic default for BRAM models
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-- 2008-03-02 122 1.0.2 change generic default for BRAM models
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-- 2007-12-27 106 1.0.1 add fifo_2c_dram
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-- 2007-12-27 106 1.0.1 add fifo_2c_dram
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AWIDTH : positive := 4; -- address width (sets size)
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AWIDTH : positive := 4; -- address width (sets size)
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DWIDTH : positive := 16); -- data width
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DWIDTH : positive := 16); -- data width
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port (
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port (
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CLKW : in slbit; -- clock (write side)
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CLKW : in slbit; -- clock (write side)
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CLKR : in slbit; -- clock (read side)
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CLKR : in slbit; -- clock (read side)
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RESETW : in slbit; -- reset (synchronous with CLKW)
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RESETW : in slbit; -- W|reset from write side
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RESETR : in slbit; -- reset (synchronous with CLKR)
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RESETR : in slbit; -- R|reset from read side
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DI : in slv(DWIDTH-1 downto 0); -- input data
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DI : in slv(DWIDTH-1 downto 0); -- W|input data
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ENA : in slbit; -- write enable
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ENA : in slbit; -- W|write enable
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BUSY : out slbit; -- write port hold
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BUSY : out slbit; -- W|write port hold
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DO : out slv(DWIDTH-1 downto 0); -- output data
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DO : out slv(DWIDTH-1 downto 0); -- R|output data
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VAL : out slbit; -- read valid
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VAL : out slbit; -- R|read valid
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HOLD : in slbit; -- read hold
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HOLD : in slbit; -- R|read hold
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SIZEW : out slv(AWIDTH-1 downto 0); -- number slots to write (synch w/ CLKW)
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SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
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SIZER : out slv(AWIDTH-1 downto 0) -- number slots to read (synch w/ CLKR)
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SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
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);
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);
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end component;
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end component;
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end package memlib;
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end package memlib;
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