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-- $Id: rritb_rbmon.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: rb_mon.vhd 346 2010-12-22 22:59:26Z mueller $
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--
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: rritb_rbmon - sim
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-- Module Name: rb_mon - sim
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-- Description: rritb: rri rbus monitor
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-- Description: rbus monitor (for tb's)
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon
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-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon
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-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon
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-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext)
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-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext)
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-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
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-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
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-- drop RP_IINT signal from interfaces
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-- drop RP_IINT signal from interfaces
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-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
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-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.simlib.all;
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use work.simlib.all;
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use work.rrilib.all;
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use work.rblib.all;
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entity rritb_rbmon is -- rritb, rri rbus monitor
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entity rb_mon is -- rbus monitor (for tb's)
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generic (
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generic (
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DBASE : positive := 2); -- base for writing data values
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DBASE : positive := 2); -- base for writing data values
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
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CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
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RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
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RB_STAT : in slv3 -- rbus: status flags
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RB_STAT : in slv3 -- rbus: status flags
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);
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);
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end rritb_rbmon;
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end rb_mon;
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architecture sim of rritb_rbmon is
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architecture sim of rb_mon is
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begin
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begin
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proc_rbmoni: process
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proc_moni: process
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variable oline : line;
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variable oline : line;
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variable nhold : integer := 0;
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variable nhold : integer := 0;
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variable data : slv16 := (others=>'0');
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variable data : slv16 := (others=>'0');
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variable tag : string(1 to 8) := (others=>' ');
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variable tag : string(1 to 8) := (others=>' ');
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variable err : slbit := '0';
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variable err : slbit := '0';
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wait until ENA='1'; -- stall process till enabled
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wait until ENA='1'; -- stall process till enabled
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end if;
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end if;
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wait until CLK'event and CLK='1'; -- check at end of clock cycle
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wait until CLK'event and CLK='1'; -- check at end of clock cycle
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if RB_MREQ.req = '1' then
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if RB_MREQ.aval='1' and (RB_MREQ.re='1' or RB_MREQ.we='1') then
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if RB_SRES.err = '1' then
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if RB_SRES.err = '1' then
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err := '1';
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err := '1';
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end if;
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end if;
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if RB_SRES.busy = '1' then
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if RB_SRES.busy = '1' then
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nhold := nhold + 1;
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nhold := nhold + 1;
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else
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else
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if RB_MREQ.req = '1' then
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data := (others=>'0');
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if RB_MREQ.we = '0' then
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tag := ": ???? ";
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if RB_MREQ.re = '1' then
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data := RB_SRES.dout;
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data := RB_SRES.dout;
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tag := ": rbre ";
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tag := ": rbre ";
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else
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end if;
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if RB_MREQ.we = '1' then
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data := RB_MREQ.din;
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data := RB_MREQ.din;
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tag := ": rbwe ";
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tag := ": rbwe ";
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end if;
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end if;
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end if;
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write_data(oline, tag, data, nhold, err='1', " ERR='1'");
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write_data(oline, tag, data, nhold, err='1', " ERR='1'");
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nhold := 0;
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nhold := 0;
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end if;
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end if;
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if unsigned(RB_LAM) /= 0 then
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if unsigned(RB_LAM) /= 0 then
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write_data(oline, ": rblam ", RB_LAM, 0, true, " RB_LAM active");
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write_data(oline, ": rblam ", RB_LAM, 0, true, " RB_LAM active");
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end if;
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end if;
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end loop;
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end loop;
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end process proc_rbmoni;
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end process proc_moni;
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end sim;
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end sim;
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