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-- $Id: rbd_timer.vhd 351 2010-12-30 21:50:54Z mueller $
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-- $Id: rbd_timer.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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--
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--
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-- Test bench: -
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-- Test bench: -
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 12.1; ghdl 0.29
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-- Tool versions: xst 12.1, 13.1; ghdl 0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-12-29 351 12.1 M53d xc3s1000-4 19 63 - 34 s 7.6
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-- 2010-12-29 351 12.1 M53d xc3s1000-4 19 63 - 34 s 7.6
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-19 427 1.0.1 now numeric_std clean
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-- 2010-12-29 351 1.0 Initial version
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-- 2010-12-29 351 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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-- rbus registers:
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-- rbus registers:
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--
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--
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-- w: if > 0 timer is running
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-- w: if > 0 timer is running
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.rblib.all;
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use work.rblib.all;
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entity rbd_timer is -- rbus dev: usec precision timer
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entity rbd_timer is -- rbus dev: usec precision timer
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generic (
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generic (
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RB_ADDR : slv8 := conv_std_logic_vector(2#00000000#,8));
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RB_ADDR : slv8 := slv(to_unsigned(2#00000000#,8)));
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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CE_USEC : in slbit; -- usec pulse
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_MREQ : in rb_mreq_type; -- rbus: request
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begin
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begin
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if CLK'event and CLK='1' then
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if rising_edge(CLK) then
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if RESET = '1' then
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if RESET = '1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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if r.timer_act = '1' then -- if timer active
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if r.timer_act = '1' then -- if timer active
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if unsigned(r.timer) = 0 then -- if timer at end
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if unsigned(r.timer) = 0 then -- if timer at end
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n.timer_act := '0'; -- mark unactive
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n.timer_act := '0'; -- mark unactive
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n.timer_end := '1'; -- send end marker
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n.timer_end := '1'; -- send end marker
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else -- else: timer not at end
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else -- else: timer not at end
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n.timer := unsigned(r.timer) - 1; -- decrement
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n.timer := slv(unsigned(r.timer) - 1); -- decrement
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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N_REGS <= n;
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N_REGS <= n;
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