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-- $Id: rlink_sp1c.vhd 641 2015-02-01 22:12:15Z mueller $
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-- $Id: rlink_sp1c.vhd 672 2015-05-02 21:58:28Z mueller $
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--
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--
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-- Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Module Name: rlink_sp1c - syn
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-- Module Name: rlink_sp1c - syn
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-- Description: rlink_core8 + serport_1clock combo
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-- Description: rlink_core8 + serport_1clock combo
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--
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--
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-- Dependencies: rlink_core8
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-- Dependencies: rlink_core8
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-- serport/serport_1clock
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-- serport/serport_1clock
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-- rbus/rbd_rbmon
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-- rbus/rb_sres_or_2
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--
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--
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-- Test bench: -
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-- Test bench: -
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
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-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
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-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
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-- 2015-05-02 672 14.7 131013 xc6slx16-2 495 671 56 255 s 8.8 - -
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-- 2011-12-09 437 13.1 O40d xc3s1000-4 337 733 64 469 s 9.8 - -
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-- 2011-12-09 437 13.1 O40d xc3s1000-4 337 733 64 469 s 9.8 - -
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2015-05-02 672 4.2 add rbd_rbmon (optional via generics)
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-- 2015-04-11 666 4.1 rename ENAESC->ESCFILL, rearrange XON handling
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-- 2014-08-28 588 4.0 use rlink v4 iface, 4 bit STAT
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-- 2014-08-28 588 4.0 use rlink v4 iface, 4 bit STAT
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-- 2011-12-09 437 1.0 Initial version
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-- 2011-12-09 437 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.rblib.all;
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use work.rblib.all;
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use work.rbdlib.all;
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use work.rlinklib.all;
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use work.rlinklib.all;
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use work.serportlib.all;
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use work.serportlib.all;
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entity rlink_sp1c is -- rlink_core8+serport_1clock combo
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entity rlink_sp1c is -- rlink_core8+serport_1clock combo
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generic (
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generic (
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OFAWIDTH : natural := 5; -- output fifo address width (0=none)
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OFAWIDTH : natural := 5; -- output fifo address width (0=none)
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ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
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ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
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ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
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ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
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ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
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ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
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CDWIDTH : positive := 13; -- clk divider width
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT : natural := 15); -- clk divider initial/reset setting
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CDINIT : natural := 15; -- clk divider initial/reset setting
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RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
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RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- 1 usec clock enable
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CE_USEC : in slbit; -- 1 usec clock enable
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CE_MSEC : in slbit; -- 1 msec clock enable
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CE_MSEC : in slbit; -- 1 msec clock enable
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CE_INT : in slbit := '0'; -- rri ato time unit clock enable
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CE_INT : in slbit := '0'; -- rri ato time unit clock enable
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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ENAXON : in slbit; -- enable xon/xoff handling
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ENAXON : in slbit; -- enable xon/xoff handling
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ENAESC : in slbit; -- enable xon/xoff escaping
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ESCFILL : in slbit; -- enable fill escaping
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RXSD : in slbit; -- receive serial data (board view)
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RXSD : in slbit; -- receive serial data (board view)
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TXSD : out slbit; -- transmit serial data (board view)
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TXSD : out slbit; -- transmit serial data (board view)
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CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
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CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
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RTS_N : out slbit; -- request to send (act.low, board view)
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RTS_N : out slbit; -- request to send (act.low, board view)
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_MREQ : out rb_mreq_type; -- rbus: request
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signal RLB_BUSY : slbit := '0';
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signal RLB_BUSY : slbit := '0';
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signal RLB_DO : slv8 := (others=>'0');
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signal RLB_DO : slv8 := (others=>'0');
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signal RLB_VAL : slbit := '0';
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signal RLB_VAL : slbit := '0';
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signal RLB_HOLD : slbit := '0';
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signal RLB_HOLD : slbit := '0';
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signal RB_MREQ_M : rb_mreq_type := rb_mreq_init;
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signal RB_SRES_M : rb_sres_type := rb_sres_init;
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signal RB_SRES_RBMON : rb_sres_type := rb_sres_init;
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begin
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begin
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CORE : rlink_core8
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CORE : rlink_core8 -- rlink master ----------------------
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generic map (
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generic map (
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BTOWIDTH => BTOWIDTH,
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BTOWIDTH => BTOWIDTH,
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RTAWIDTH => RTAWIDTH,
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RTAWIDTH => RTAWIDTH,
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SYSID => SYSID,
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SYSID => SYSID,
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ENAPIN_RLMON => ENAPIN_RLMON,
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ENAPIN_RLMON => ENAPIN_RLMON,
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ENAPIN_RBMON => ENAPIN_RBMON)
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ENAPIN_RBMON => ENAPIN_RBMON)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_INT => CE_INT,
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CE_INT => CE_INT,
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RESET => RESET,
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RESET => RESET,
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ESCXON => ENAXON,
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ESCFILL => ESCFILL,
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RLB_DI => RLB_DI,
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RLB_DI => RLB_DI,
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RLB_ENA => RLB_ENA,
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RLB_ENA => RLB_ENA,
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RLB_BUSY => RLB_BUSY,
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RLB_BUSY => RLB_BUSY,
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RLB_DO => RLB_DO,
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RLB_DO => RLB_DO,
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RLB_VAL => RLB_VAL,
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RLB_VAL => RLB_VAL,
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RLB_HOLD => RLB_HOLD,
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RLB_HOLD => RLB_HOLD,
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RL_MONI => RL_MONI,
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RL_MONI => RL_MONI,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ_M,
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RB_SRES => RB_SRES,
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RB_SRES => RB_SRES_M,
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RB_LAM => RB_LAM,
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RB_LAM => RB_LAM,
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RB_STAT => RB_STAT
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RB_STAT => RB_STAT
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);
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);
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SERPORT : serport_1clock
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SERPORT : serport_1clock -- serport interface -----------------
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generic map (
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generic map (
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CDWIDTH => CDWIDTH,
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CDWIDTH => CDWIDTH,
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CDINIT => CDINIT,
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CDINIT => CDINIT,
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RXFAWIDTH => IFAWIDTH,
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RXFAWIDTH => IFAWIDTH,
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TXFAWIDTH => OFAWIDTH)
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TXFAWIDTH => OFAWIDTH)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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RESET => RESET,
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RESET => RESET,
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ENAXON => ENAXON,
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ENAXON => ENAXON,
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ENAESC => ENAESC,
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ENAESC => '0', -- escaping now in rlink_core8
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RXDATA => RLB_DI,
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RXDATA => RLB_DI,
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RXVAL => RLB_ENA,
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RXVAL => RLB_ENA,
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RXHOLD => RLB_BUSY,
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RXHOLD => RLB_BUSY,
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TXDATA => RLB_DO,
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TXDATA => RLB_DO,
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TXENA => RLB_VAL,
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TXENA => RLB_VAL,
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Line 149... |
TXSD => TXSD,
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TXSD => TXSD,
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RXRTS_N => RTS_N,
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RXRTS_N => RTS_N,
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TXCTS_N => CTS_N
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TXCTS_N => CTS_N
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);
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);
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RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor --------------
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begin
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I0 : rbd_rbmon
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generic map (
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RB_ADDR => RBMON_RBADDR,
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AWIDTH => RBMON_AWIDTH)
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port map (
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CLK => CLK,
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RESET => RESET,
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RB_MREQ => RB_MREQ_M,
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RB_SRES => RB_SRES_RBMON,
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RB_SRES_SUM => RB_SRES_M
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);
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end generate RBMON;
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RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
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port map (
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RB_SRES_1 => RB_SRES,
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RB_SRES_2 => RB_SRES_RBMON,
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RB_SRES_OR => RB_SRES_M
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);
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RB_MREQ <= RB_MREQ_M; -- setup output signals
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end syn;
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end syn;
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No newline at end of file
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No newline at end of file
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