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-- $Id: serport_uart_rxtx_ab.vhd 476 2013-01-26 22:23:53Z mueller $
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-- $Id: serport_uart_rxtx_ab.vhd 641 2015-02-01 22:12:15Z mueller $
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--
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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--
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--
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-- Dependencies: serport_uart_autobaud
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-- Dependencies: serport_uart_autobaud
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-- serport_uart_rxtx
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-- serport_uart_rxtx
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-12-25 348 12.1 M53d xc3s1000-4 99 197 - 124 s 9.8
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-- 2010-12-25 348 12.1 M53d xc3s1000-4 99 197 - 124 s 9.8
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2015-02-01 641 1.2 add CLKDIV_F for autobaud;
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-- 2011-10-22 417 1.1.1 now numeric_std clean
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-- 2011-10-22 417 1.1.1 now numeric_std clean
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-- 2010-12-26 348 1.1 add ABCLKDIV port for clock divider setting
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-- 2010-12-26 348 1.1 add ABCLKDIV port for clock divider setting
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-- 2007-06-24 60 1.0 Initial version
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-- 2007-06-24 60 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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TXDATA : in slv8; -- transmit data in
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit; -- transmit busy
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TXBUSY : out slbit; -- transmit busy
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ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
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ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
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ABDONE : out slbit; -- autobaud resync done
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ABDONE : out slbit; -- autobaud resync done
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ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting
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ABCLKDIV : out slv(CDWIDTH-1 downto 0); -- autobaud clock divider setting
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ABCLKDIV_F : out slv3 -- autobaud clock divider fraction
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);
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);
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end serport_uart_rxtx_ab;
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end serport_uart_rxtx_ab;
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architecture syn of serport_uart_rxtx_ab is
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architecture syn of serport_uart_rxtx_ab is
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signal CLKDIV : slv(CDWIDTH-1 downto 0) := slv(to_unsigned(0, CDWIDTH));
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signal CLKDIV : slv(CDWIDTH-1 downto 0) := slv(to_unsigned(0, CDWIDTH));
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signal CLKDIV_F : slv3 := (others=>'0');
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signal ABACT_L : slbit := '0'; -- local readable copy of ABACT
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signal ABACT_L : slbit := '0'; -- local readable copy of ABACT
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signal UART_RESET : slbit := '0';
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signal UART_RESET : slbit := '0';
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begin
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begin
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CLK => CLK,
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CLK => CLK,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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RESET => RESET,
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RESET => RESET,
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RXSD => RXSD,
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RXSD => RXSD,
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CLKDIV => CLKDIV,
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CLKDIV => CLKDIV,
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CLKDIV_F => CLKDIV_F,
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ACT => ABACT_L,
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ACT => ABACT_L,
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DONE => ABDONE
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DONE => ABDONE
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);
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);
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UART_RESET <= ABACT_L or RESET;
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UART_RESET <= ABACT_L or RESET;
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ABACT <= ABACT_L;
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ABACT <= ABACT_L;
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ABCLKDIV <= CLKDIV;
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ABCLKDIV <= CLKDIV;
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ABCLKDIV_F <= CLKDIV_F;
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RXTX : serport_uart_rxtx
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RXTX : serport_uart_rxtx
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generic map (
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generic map (
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CDWIDTH => CDWIDTH)
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CDWIDTH => CDWIDTH)
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port map (
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port map (
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