| Line 1... |
Line 1... |
-- $Id: serport_uart_rxtx_ab.vhd 314 2010-07-09 17:38:41Z mueller $
|
-- $Id: serport_uart_rxtx_ab.vhd 350 2010-12-28 16:40:11Z mueller $
|
--
|
--
|
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
--
|
--
|
-- This program is free software; you may redistribute and/or modify it under
|
-- This program is free software; you may redistribute and/or modify it under
|
-- the terms of the GNU General Public License as published by the Free
|
-- the terms of the GNU General Public License as published by the Free
|
-- Software Foundation, either version 2, or at your option any later version.
|
-- Software Foundation, either version 2, or at your option any later version.
|
--
|
--
|
| Line 17... |
Line 17... |
--
|
--
|
-- Dependencies: serport_uart_autobaud
|
-- Dependencies: serport_uart_autobaud
|
-- serport_uart_rxtx
|
-- serport_uart_rxtx
|
-- Test bench: -
|
-- Test bench: -
|
-- Target Devices: generic
|
-- Target Devices: generic
|
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
|
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
|
|
--
|
|
-- Synthesized (xst):
|
|
-- Date Rev ise Target flop lutl lutm slic t peri
|
|
-- 2010-12-25 348 12.1 M53d xc3s1000-4 99 197 - 124 s 9.8
|
|
--
|
-- Revision History:
|
-- Revision History:
|
-- Date Rev Version Comment
|
-- Date Rev Version Comment
|
|
-- 2010-12-26 348 1.1 add ABCLKDIV port for clock divider setting
|
-- 2007-06-24 60 1.0 Initial version
|
-- 2007-06-24 60 1.0 Initial version
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
| Line 48... |
Line 54... |
TXSD : out slbit; -- transmit serial data (uart view)
|
TXSD : out slbit; -- transmit serial data (uart view)
|
TXDATA : in slv8; -- transmit data in
|
TXDATA : in slv8; -- transmit data in
|
TXENA : in slbit; -- transmit data enable
|
TXENA : in slbit; -- transmit data enable
|
TXBUSY : out slbit; -- transmit busy
|
TXBUSY : out slbit; -- transmit busy
|
ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
|
ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
|
ABDONE : out slbit -- autobaud resync done
|
ABDONE : out slbit; -- autobaud resync done
|
|
ABCLKDIV : out slv(CDWIDTH-1 downto 0) -- autobaud clock divider setting
|
);
|
);
|
end serport_uart_rxtx_ab;
|
end serport_uart_rxtx_ab;
|
|
|
architecture syn of serport_uart_rxtx_ab is
|
architecture syn of serport_uart_rxtx_ab is
|
|
|
| Line 76... |
Line 83... |
DONE => ABDONE
|
DONE => ABDONE
|
);
|
);
|
|
|
UART_RESET <= ABACT_L or RESET;
|
UART_RESET <= ABACT_L or RESET;
|
ABACT <= ABACT_L;
|
ABACT <= ABACT_L;
|
|
ABCLKDIV <= CLKDIV;
|
|
|
RXTX : serport_uart_rxtx
|
RXTX : serport_uart_rxtx
|
generic map (
|
generic map (
|
CDWIDTH => CDWIDTH)
|
CDWIDTH => CDWIDTH)
|
port map (
|
port map (
|
