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-- $Id: pdp11_mem70.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: pdp11_mem70.vhd 333 2010-10-17 21:18:33Z mueller $
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--
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--
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-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Description: pdp11: 11/70 memory system registers
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-- Description: pdp11: 11/70 memory system registers
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-10-17 333 1.1 use ibus V2 interface
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-- 2008-08-22 161 1.0.2 rename ubf_ -> ibf_; use iblib
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-- 2008-08-22 161 1.0.2 rename ubf_ -> ibf_; use iblib
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-- 2008-02-23 118 1.0.1 use sys_conf_mem_losize; rename CACHE_ENA->_FMISS
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-- 2008-02-23 118 1.0.1 use sys_conf_mem_losize; rename CACHE_ENA->_FMISS
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-- 2008-01-27 115 1.0 Initial version
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-- 2008-01-27 115 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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subtype cntl_ibf_fmiss is integer range 3 downto 2;
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subtype cntl_ibf_fmiss is integer range 3 downto 2;
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constant cntl_ibf_disutrap : integer := 1;
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constant cntl_ibf_disutrap : integer := 1;
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constant cntl_ibf_distrap : integer := 0;
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constant cntl_ibf_distrap : integer := 0;
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type regs_type is record -- state registers
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type regs_type is record -- state registers
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ibsel_cr : slbit; -- ibus select cntl
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ibsel_hm : slbit; -- ibus select hitmiss
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ibsel_ls : slbit; -- ibus select losize
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ibsel_nn : slbit; -- ibus select others
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hm_data : slv6; -- hit/miss: data
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hm_data : slv6; -- hit/miss: data
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cr_frep : slv2; -- cntl: force replacement bits
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cr_frep : slv2; -- cntl: force replacement bits
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cr_fmiss : slv2; -- cntl: force miss bits
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cr_fmiss : slv2; -- cntl: force miss bits
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cr_disutrap: slbit; -- cntl: disable unibus trap
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cr_disutrap: slbit; -- cntl: disable unibus trap
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cr_distrap: slbit; -- cntl: disable traps
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cr_distrap: slbit; -- cntl: disable traps
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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'0','0','0','0', -- ibsel_*
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(others=>'0'), -- hm_data
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(others=>'0'), -- hm_data
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"00","00", -- cr_freq,_fmiss
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"00","00", -- cr_freq,_fmiss
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'0','0' -- dis(u)trap
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'0','0' -- dis(u)trap
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);
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);
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end process proc_regs;
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end process proc_regs;
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proc_next: process (R_REGS, HM_ENA, HM_VAL, IB_MREQ)
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proc_next: process (R_REGS, HM_ENA, HM_VAL, IB_MREQ)
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable ibsel_cr : slbit := '0'; -- control reg
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variable ibsel_hm : slbit := '0'; -- hit/miss reg
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variable ibsel_ls : slbit := '0'; -- low size reg
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variable ibsel_nn : slbit := '0'; -- all other
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variable ibsel : slbit := '0';
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variable idout : slv16 := (others=>'0');
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variable idout : slv16 := (others=>'0');
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variable ibreq : slbit := '0';
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variable ibw0 : slbit := '0';
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begin
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begin
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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ibsel_cr := '0';
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ibsel_hm := '0';
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ibsel_ls := '0';
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ibsel_nn := '0';
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ibsel := '0';
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idout := (others=>'0');
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idout := (others=>'0');
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ibreq := IB_MREQ.re or IB_MREQ.we;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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if IB_MREQ.req = '1' then
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-- ibus address decoder
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n.ibsel_cr := '0';
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n.ibsel_hm := '0';
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n.ibsel_ls := '0';
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n.ibsel_nn := '0';
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if IB_MREQ.aval = '1' then
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if IB_MREQ.addr = ibaddr_cntl(12 downto 1) then
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if IB_MREQ.addr = ibaddr_cntl(12 downto 1) then
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ibsel_cr := '1';
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n.ibsel_cr := '1';
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end if;
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end if;
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if IB_MREQ.addr = ibaddr_hm(12 downto 1) then
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if IB_MREQ.addr = ibaddr_hm(12 downto 1) then
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ibsel_hm := '1';
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n.ibsel_hm := '1';
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end if;
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end if;
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if IB_MREQ.addr = ibaddr_losize(12 downto 1) then
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if IB_MREQ.addr = ibaddr_losize(12 downto 1) then
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ibsel_ls := '1';
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n.ibsel_ls := '1';
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end if;
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end if;
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if IB_MREQ.addr=ibaddr_loaddr(12 downto 1) or
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if IB_MREQ.addr=ibaddr_loaddr(12 downto 1) or
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IB_MREQ.addr=ibaddr_hiaddr(12 downto 1) or
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IB_MREQ.addr=ibaddr_hiaddr(12 downto 1) or
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IB_MREQ.addr=ibaddr_syserr(12 downto 1) or
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IB_MREQ.addr=ibaddr_syserr(12 downto 1) or
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IB_MREQ.addr=ibaddr_maint(12 downto 1) or
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IB_MREQ.addr=ibaddr_maint(12 downto 1) or
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IB_MREQ.addr=ibaddr_hisize(12 downto 1) then
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IB_MREQ.addr=ibaddr_hisize(12 downto 1) then
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ibsel_nn := '1';
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n.ibsel_nn := '1';
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end if;
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end if;
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end if;
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end if;
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ibsel := ibsel_cr or ibsel_hm or ibsel_ls or ibsel_nn;
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-- ibus transactions
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if r.ibsel_cr = '1' then
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if ibsel_cr = '1' then
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idout(cntl_ibf_frep) := r.cr_frep;
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idout(cntl_ibf_frep) := r.cr_frep;
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idout(cntl_ibf_fmiss) := r.cr_fmiss;
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idout(cntl_ibf_fmiss) := r.cr_fmiss;
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idout(cntl_ibf_disutrap) := r.cr_disutrap;
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idout(cntl_ibf_disutrap) := r.cr_disutrap;
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idout(cntl_ibf_distrap) := r.cr_distrap;
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idout(cntl_ibf_distrap) := r.cr_distrap;
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end if;
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end if;
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if ibsel_hm = '1' then
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if r.ibsel_hm = '1' then
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idout(r.hm_data'range) := r.hm_data;
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idout(r.hm_data'range) := r.hm_data;
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end if;
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end if;
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if ibsel_ls = '1' then
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if r.ibsel_ls = '1' then
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idout := conv_std_logic_vector(sys_conf_mem_losize,16);
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idout := conv_std_logic_vector(sys_conf_mem_losize,16);
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end if;
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end if;
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if ibsel_cr='1' and IB_MREQ.we='1' and IB_MREQ.be0='1' then
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if r.ibsel_cr='1' and ibw0='1' then
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n.cr_frep := IB_MREQ.din(cntl_ibf_frep);
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n.cr_frep := IB_MREQ.din(cntl_ibf_frep);
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n.cr_fmiss := IB_MREQ.din(cntl_ibf_fmiss);
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n.cr_fmiss := IB_MREQ.din(cntl_ibf_fmiss);
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n.cr_disutrap := IB_MREQ.din(cntl_ibf_disutrap);
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n.cr_disutrap := IB_MREQ.din(cntl_ibf_disutrap);
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n.cr_distrap := IB_MREQ.din(cntl_ibf_distrap);
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n.cr_distrap := IB_MREQ.din(cntl_ibf_distrap);
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end if;
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end if;
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n.hm_data := r.hm_data(r.hm_data'left-1 downto 0) & HM_VAL;
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n.hm_data := r.hm_data(r.hm_data'left-1 downto 0) & HM_VAL;
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end if;
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end if;
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N_REGS <= n;
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N_REGS <= n;
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IB_SRES.ack <= ibsel;
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IB_SRES.busy <= '0';
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IB_SRES.dout <= idout;
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IB_SRES.dout <= idout;
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IB_SRES.ack <= (r.ibsel_cr or r.ibsel_hm or
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r.ibsel_ls or r.ibsel_nn) and ibreq;
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IB_SRES.busy <= '0';
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end process proc_next;
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end process proc_next;
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CACHE_FMISS <= (R_REGS.cr_fmiss(1) or R_REGS.cr_fmiss(0));
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CACHE_FMISS <= (R_REGS.cr_fmiss(1) or R_REGS.cr_fmiss(0));
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